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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 118

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Rev Log message Author Age Path
118 The top level name was in uppercase. The correct is lowercase. creep 5870d 12h /t6507lp/trunk/rtl/verilog/
117 Fixed the top level and connected the entire project. creep 5870d 12h /t6507lp/trunk/rtl/verilog/
116 Changed the module instantiation into the dot form. creep 5870d 12h /t6507lp/trunk/rtl/verilog/
115 Renamed the signal control. It is mem_rw now. creep 5870d 13h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5870d 13h /t6507lp/trunk/rtl/verilog/
113 Timescale was unified. gabrieloshiro 5870d 13h /t6507lp/trunk/rtl/verilog/
112 Created a global timescale file for the project. creep 5870d 13h /t6507lp/trunk/rtl/verilog/
111 Performed some linting after coding was finished. creep 5871d 04h /t6507lp/trunk/rtl/verilog/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5871d 06h /t6507lp/trunk/rtl/verilog/
109 PLA and PLP are coded and simulated. creep 5871d 08h /t6507lp/trunk/rtl/verilog/
108 PHA and PHP are coded and simulated. creep 5871d 09h /t6507lp/trunk/rtl/verilog/
107 The RTS instruction is working fine. Coded and simulated. creep 5871d 10h /t6507lp/trunk/rtl/verilog/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5871d 10h /t6507lp/trunk/rtl/verilog/
105 The RTI instruction is working fine. Coded and simulated. creep 5871d 10h /t6507lp/trunk/rtl/verilog/
104 The BRK instruction is working. The reset vector was tested also. creep 5871d 12h /t6507lp/trunk/rtl/verilog/
103 Some early modifications to support the special stack instructions. creep 5872d 06h /t6507lp/trunk/rtl/verilog/
102 Some early modifications to support the special stack instructions. creep 5872d 09h /t6507lp/trunk/rtl/verilog/
101 Absolute indirect addressing mode is coded and simulated. creep 5872d 12h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5872d 13h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 5872d 14h /t6507lp/trunk/rtl/verilog/

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