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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 160

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Rev Log message Author Age Path
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5870d 18h /t6507lp/trunk/rtl/verilog/
157 gabrieloshiro 5870d 19h /t6507lp/trunk/rtl/verilog/
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5870d 20h /t6507lp/trunk/rtl/verilog/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5871d 01h /t6507lp/trunk/rtl/verilog/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 5871d 18h /t6507lp/trunk/rtl/verilog/
152 Bug #24 from trac was fixed. gabrieloshiro 5871d 19h /t6507lp/trunk/rtl/verilog/
151 tah comitado! gabrieloshiro 5871d 20h /t6507lp/trunk/rtl/verilog/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5871d 20h /t6507lp/trunk/rtl/verilog/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5871d 21h /t6507lp/trunk/rtl/verilog/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5871d 21h /t6507lp/trunk/rtl/verilog/
146 Fixed ticket #13: reset behavior in the FSM. creep 5872d 17h /t6507lp/trunk/rtl/verilog/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5872d 20h /t6507lp/trunk/rtl/verilog/
144 Checker is working fine. Hunting bugs... creep 5872d 20h /t6507lp/trunk/rtl/verilog/
143 Modified the inputs so the alu resets. creep 5872d 21h /t6507lp/trunk/rtl/verilog/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5872d 23h /t6507lp/trunk/rtl/verilog/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5873d 00h /t6507lp/trunk/rtl/verilog/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5873d 00h /t6507lp/trunk/rtl/verilog/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5873d 00h /t6507lp/trunk/rtl/verilog/
136 Some minor coding style changes. gabrieloshiro 5873d 20h /t6507lp/trunk/rtl/verilog/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5877d 19h /t6507lp/trunk/rtl/verilog/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5877d 23h /t6507lp/trunk/rtl/verilog/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5878d 00h /t6507lp/trunk/rtl/verilog/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5878d 00h /t6507lp/trunk/rtl/verilog/
120 Added some extra commentaries. creep 5879d 20h /t6507lp/trunk/rtl/verilog/
119 removing old file. creep 5879d 22h /t6507lp/trunk/rtl/verilog/
118 The top level name was in uppercase. The correct is lowercase. creep 5880d 00h /t6507lp/trunk/rtl/verilog/
117 Fixed the top level and connected the entire project. creep 5880d 00h /t6507lp/trunk/rtl/verilog/
116 Changed the module instantiation into the dot form. creep 5880d 00h /t6507lp/trunk/rtl/verilog/
115 Renamed the signal control. It is mem_rw now. creep 5880d 00h /t6507lp/trunk/rtl/verilog/
114 Created a global timescale file for the project. Added to the top module. creep 5880d 01h /t6507lp/trunk/rtl/verilog/

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