OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 169

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
169 ADC bugs finally fixed. gabrieloshiro 5727d 19h /t6507lp/trunk/rtl/verilog/
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5727d 20h /t6507lp/trunk/rtl/verilog/
167 Now SBC is supposed to work. gabrieloshiro 5727d 21h /t6507lp/trunk/rtl/verilog/
166 Commiting again! gabrieloshiro 5727d 21h /t6507lp/trunk/rtl/verilog/
165 SBC and PHP fixed! gabrieloshiro 5727d 21h /t6507lp/trunk/rtl/verilog/
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5727d 22h /t6507lp/trunk/rtl/verilog/
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5727d 23h /t6507lp/trunk/rtl/verilog/
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5727d 23h /t6507lp/trunk/rtl/verilog/
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5728d 00h /t6507lp/trunk/rtl/verilog/
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5730d 20h /t6507lp/trunk/rtl/verilog/
157 gabrieloshiro 5730d 21h /t6507lp/trunk/rtl/verilog/
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5730d 22h /t6507lp/trunk/rtl/verilog/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5731d 03h /t6507lp/trunk/rtl/verilog/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 5731d 20h /t6507lp/trunk/rtl/verilog/
152 Bug #24 from trac was fixed. gabrieloshiro 5731d 21h /t6507lp/trunk/rtl/verilog/
151 tah comitado! gabrieloshiro 5731d 22h /t6507lp/trunk/rtl/verilog/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5731d 22h /t6507lp/trunk/rtl/verilog/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5731d 23h /t6507lp/trunk/rtl/verilog/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5731d 23h /t6507lp/trunk/rtl/verilog/
146 Fixed ticket #13: reset behavior in the FSM. creep 5732d 19h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.