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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 195

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Rev Log message Author Age Path
195 FSM was locking on TSX/TXS. creep 5813d 18h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5813d 20h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5814d 15h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5814d 17h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5819d 20h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5819d 21h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5820d 14h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5820d 14h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5820d 14h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5827d 13h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5827d 21h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 5828d 14h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5828d 17h /t6507lp/trunk/rtl/verilog/
179 STA, STY and STX fixed gabrieloshiro 5828d 19h /t6507lp/trunk/rtl/verilog/
178 STA, STY and STX fixed gabrieloshiro 5828d 19h /t6507lp/trunk/rtl/verilog/
176 RTI works for me gabrieloshiro 5828d 22h /t6507lp/trunk/rtl/verilog/
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5829d 18h /t6507lp/trunk/rtl/verilog/
174 SBC borrow flag bug fixed... again gabrieloshiro 5829d 18h /t6507lp/trunk/rtl/verilog/
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5829d 19h /t6507lp/trunk/rtl/verilog/
172 RTI supported to be compatible with stella gabrieloshiro 5829d 21h /t6507lp/trunk/rtl/verilog/

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