OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 198

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
198 Removed the old I/O file creep 6167d 06h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 6167d 06h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 6167d 23h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 6168d 03h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 6168d 05h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 6169d 00h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 6169d 02h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 6174d 05h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 6174d 05h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 6174d 22h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 6174d 22h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 6174d 22h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 6181d 22h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 6182d 06h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 6182d 22h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 6183d 01h /t6507lp/trunk/rtl/verilog/
179 STA, STY and STX fixed gabrieloshiro 6183d 04h /t6507lp/trunk/rtl/verilog/
178 STA, STY and STX fixed gabrieloshiro 6183d 04h /t6507lp/trunk/rtl/verilog/
176 RTI works for me gabrieloshiro 6183d 07h /t6507lp/trunk/rtl/verilog/
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 6184d 03h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.