OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 205

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 6113d 22h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 6113d 23h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 6114d 03h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 6116d 21h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 6116d 22h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 6117d 01h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 6117d 01h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 6117d 04h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 6117d 04h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 6117d 21h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 6118d 01h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 6118d 03h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 6118d 22h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 6119d 00h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 6124d 03h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 6124d 03h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 6124d 20h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 6124d 20h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 6124d 20h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 6131d 20h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.