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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 211

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Rev Log message Author Age Path
211 Added the keyboard controller testbench to the repository creep 6073d 12h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 6076d 05h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 6076d 06h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 6076d 10h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 6079d 04h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 6079d 05h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 6079d 08h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 6079d 08h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 6079d 11h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 6079d 11h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 6080d 04h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 6080d 08h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 6080d 10h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 6081d 05h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 6081d 07h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 6086d 10h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 6086d 10h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 6087d 03h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 6087d 03h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 6087d 03h /t6507lp/trunk/rtl/verilog/

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