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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 211

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Rev Log message Author Age Path
211 Added the keyboard controller testbench to the repository creep 5843d 17h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5846d 10h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5846d 12h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5846d 16h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5849d 10h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5849d 11h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 5849d 13h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 5849d 14h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 5849d 16h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5849d 16h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5850d 10h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5850d 13h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5850d 16h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5851d 11h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5851d 12h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5856d 16h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5856d 16h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5857d 09h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5857d 09h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5857d 09h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5864d 08h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5864d 17h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 5865d 09h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5865d 12h /t6507lp/trunk/rtl/verilog/
179 STA, STY and STX fixed gabrieloshiro 5865d 15h /t6507lp/trunk/rtl/verilog/
178 STA, STY and STX fixed gabrieloshiro 5865d 15h /t6507lp/trunk/rtl/verilog/
176 RTI works for me gabrieloshiro 5865d 18h /t6507lp/trunk/rtl/verilog/
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5866d 13h /t6507lp/trunk/rtl/verilog/
174 SBC borrow flag bug fixed... again gabrieloshiro 5866d 14h /t6507lp/trunk/rtl/verilog/
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5866d 14h /t6507lp/trunk/rtl/verilog/

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