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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 217

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Rev Log message Author Age Path
217 All write operations at the TIA are coded. creep 5761d 21h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 5762d 17h /t6507lp/trunk/rtl/verilog/
215 Adding the video module. creep 5763d 18h /t6507lp/trunk/rtl/verilog/
214 Added the keyboard controller to the 2600.v top level file. creep 5763d 22h /t6507lp/trunk/rtl/verilog/
212 Bug #56: ZPX page crossing. creep 5768d 22h /t6507lp/trunk/rtl/verilog/
211 Added the keyboard controller testbench to the repository creep 5768d 23h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5771d 16h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5771d 17h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5771d 22h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5774d 15h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5774d 16h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 5774d 19h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 5774d 19h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 5774d 22h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5774d 22h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5775d 15h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5775d 19h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5775d 21h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5776d 16h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5776d 18h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5781d 21h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5781d 21h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5782d 14h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 5782d 14h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 5782d 14h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 5789d 14h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5789d 22h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 5790d 14h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5790d 17h /t6507lp/trunk/rtl/verilog/
179 STA, STY and STX fixed gabrieloshiro 5790d 20h /t6507lp/trunk/rtl/verilog/

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