URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 217

Rev	Log message	Author	Age	Path
191	Added the testbench for the bus controller.	creep	6049d 10h	/t6507lp/trunk/rtl/verilog/
190	Bus controller is now linted.	creep	6049d 10h	/t6507lp/trunk/rtl/verilog/
189	Added the bus controller module.	creep	6050d 03h	/t6507lp/trunk/rtl/verilog/
188	Added the atari toplevel	creep	6050d 03h	/t6507lp/trunk/rtl/verilog/
187	Fixed the module name.	creep	6050d 03h	/t6507lp/trunk/rtl/verilog/
186	Testbench has a lot of new tests.	gabrieloshiro	6057d 02h	/t6507lp/trunk/rtl/verilog/
184	TXA and TYA behavior were changed. Now alu_result dont receive A value	gabrieloshiro	6057d 11h	/t6507lp/trunk/rtl/verilog/
183	STA, STY and STX should be working now	gabrieloshiro	6058d 03h	/t6507lp/trunk/rtl/verilog/
181	This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior	gabrieloshiro	6058d 06h	/t6507lp/trunk/rtl/verilog/
179	STA, STY and STX fixed	gabrieloshiro	6058d 08h	/t6507lp/trunk/rtl/verilog/