OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 218

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
218 Added the video converter. creep 6026d 01h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 6027d 07h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 6028d 03h /t6507lp/trunk/rtl/verilog/
215 Adding the video module. creep 6029d 04h /t6507lp/trunk/rtl/verilog/
214 Added the keyboard controller to the 2600.v top level file. creep 6029d 08h /t6507lp/trunk/rtl/verilog/
212 Bug #56: ZPX page crossing. creep 6034d 08h /t6507lp/trunk/rtl/verilog/
211 Added the keyboard controller testbench to the repository creep 6034d 09h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 6037d 02h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 6037d 03h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 6037d 07h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 6040d 01h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 6040d 02h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 6040d 05h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 6040d 05h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 6040d 08h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 6040d 08h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 6041d 01h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 6041d 05h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 6041d 07h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 6042d 02h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 6042d 04h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 6047d 07h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 6047d 07h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 6048d 00h /t6507lp/trunk/rtl/verilog/
188 Added the atari toplevel creep 6048d 00h /t6507lp/trunk/rtl/verilog/
187 Fixed the module name. creep 6048d 00h /t6507lp/trunk/rtl/verilog/
186 Testbench has a lot of new tests. gabrieloshiro 6055d 00h /t6507lp/trunk/rtl/verilog/
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 6055d 08h /t6507lp/trunk/rtl/verilog/
183 STA, STY and STX should be working now gabrieloshiro 6056d 00h /t6507lp/trunk/rtl/verilog/
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 6056d 03h /t6507lp/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.