URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 235

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Rev	Log message	Author	Age	Path
235	Bug #60: added a brief simulation to the video_converter module.	creep	6016d 13h	/t6507lp/trunk/rtl/verilog/
234	SBC Decimal mode 100% verified.	creep	6021d 15h	/t6507lp/trunk/rtl/verilog/
233	ADC and SBC are 100% verified in regular mode. Decimal mode still missing.	creep	6021d 19h	/t6507lp/trunk/rtl/verilog/
232	New video test.	creep	6023d 13h	/t6507lp/trunk/rtl/verilog/
231	Minor bugs fixed.	gabrieloshiro	6023d 15h	/t6507lp/trunk/rtl/verilog/
230	Changed TIA behavior. It is now pixel-based.	creep	6023d 15h	/t6507lp/trunk/rtl/verilog/
229	Created a one-line pattern.	creep	6023d 20h	/t6507lp/trunk/rtl/verilog/
228		gabrieloshiro	6023d 20h	/t6507lp/trunk/rtl/verilog/
227	Fixing conflicts.	creep	6023d 20h	/t6507lp/trunk/rtl/verilog/
226	work plz	creep	6023d 20h	/t6507lp/trunk/rtl/verilog/
225	Minor changes!	gabrieloshiro	6024d 12h	/t6507lp/trunk/rtl/verilog/
224	Added a top level for the tests.	creep	6024d 14h	/t6507lp/trunk/rtl/verilog/
223	Minor sintax errors fixed.	gabrieloshiro	6024d 15h	/t6507lp/trunk/rtl/verilog/
222	Added a simple line-by-line tester.	creep	6024d 16h	/t6507lp/trunk/rtl/verilog/
221	Added a VGA controller.	creep	6024d 20h	/t6507lp/trunk/rtl/verilog/
220	Bug #59: video converter done.	creep	6025d 14h	/t6507lp/trunk/rtl/verilog/
219	Video YPbPr to RGB is coded.	creep	6028d 13h	/t6507lp/trunk/rtl/verilog/
218	Added the video converter.	creep	6028d 14h	/t6507lp/trunk/rtl/verilog/
217	All write operations at the TIA are coded.	creep	6029d 19h	/t6507lp/trunk/rtl/verilog/
216	Register bank at TIA properly set. Working on the R/W instructions.	creep	6030d 15h	/t6507lp/trunk/rtl/verilog/

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 235

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