OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 236

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
236 Added the video converter testbench to the repository. creep 5677d 05h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 5677d 23h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 5683d 01h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5683d 05h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 5684d 23h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 5685d 00h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 5685d 00h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 5685d 05h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 5685d 05h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 5685d 05h /t6507lp/trunk/rtl/verilog/
226 work plz creep 5685d 05h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 5685d 21h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 5685d 23h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5686d 00h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5686d 02h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5686d 05h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 5687d 00h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 5689d 22h /t6507lp/trunk/rtl/verilog/
218 Added the video converter. creep 5689d 23h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 5691d 05h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.