OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 236

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
236 Added the video converter testbench to the repository. creep 5726d 17h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 5727d 10h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 5732d 12h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5732d 16h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 5734d 10h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 5734d 12h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 5734d 12h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 5734d 16h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 5734d 17h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 5734d 17h /t6507lp/trunk/rtl/verilog/
226 work plz creep 5734d 17h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 5735d 09h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 5735d 11h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5735d 11h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5735d 13h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5735d 17h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 5736d 11h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 5739d 10h /t6507lp/trunk/rtl/verilog/
218 Added the video converter. creep 5739d 10h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 5740d 16h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 5741d 12h /t6507lp/trunk/rtl/verilog/
215 Adding the video module. creep 5742d 13h /t6507lp/trunk/rtl/verilog/
214 Added the keyboard controller to the 2600.v top level file. creep 5742d 16h /t6507lp/trunk/rtl/verilog/
212 Bug #56: ZPX page crossing. creep 5747d 17h /t6507lp/trunk/rtl/verilog/
211 Added the keyboard controller testbench to the repository creep 5747d 17h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5750d 11h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5750d 12h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5750d 16h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5753d 10h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5753d 11h /t6507lp/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.