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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 242

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Rev Log message Author Age Path
242 Bug regardind the STA_IDY opcode creep 5669d 21h /t6507lp/trunk/rtl/verilog/
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 5670d 23h /t6507lp/trunk/rtl/verilog/
238 ALU file is linted. creep 5673d 20h /t6507lp/trunk/rtl/verilog/
237 Added a preliminary collision detection logic. creep 5674d 22h /t6507lp/trunk/rtl/verilog/
236 Added the video converter testbench to the repository. creep 5675d 01h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 5675d 18h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 5680d 20h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5681d 00h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 5682d 18h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 5682d 20h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 5682d 20h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 5683d 01h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 5683d 01h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 5683d 01h /t6507lp/trunk/rtl/verilog/
226 work plz creep 5683d 01h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 5683d 17h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 5683d 19h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5683d 20h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5683d 21h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5684d 01h /t6507lp/trunk/rtl/verilog/

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