URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 253

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Rev	Log message	Author	Age	Path
253	Changed the rw_mem signal name in the hierarchy	creep	5730d 19h	/t6507lp/trunk/rtl/verilog/
252	Added a stubs file for the pads.	creep	5730d 19h	/t6507lp/trunk/rtl/verilog/
251	Added the io wrapper	creep	5730d 22h	/t6507lp/trunk/rtl/verilog/
246	Added some older files plus the first syn script	creep	5737d 22h	/t6507lp/trunk/rtl/verilog/
243	Fixing STA_IDY bug	creep	5779d 14h	/t6507lp/trunk/rtl/verilog/
242	Bug regardind the STA_IDY opcode	creep	5779d 18h	/t6507lp/trunk/rtl/verilog/
239	Zero flag fixed for SBC while in Decimal Mode. Bug #34.	gabrieloshiro	5780d 20h	/t6507lp/trunk/rtl/verilog/
238	ALU file is linted.	creep	5783d 17h	/t6507lp/trunk/rtl/verilog/
237	Added a preliminary collision detection logic.	creep	5784d 18h	/t6507lp/trunk/rtl/verilog/
236	Added the video converter testbench to the repository.	creep	5784d 22h	/t6507lp/trunk/rtl/verilog/
235	Bug #60: added a brief simulation to the video_converter module.	creep	5785d 15h	/t6507lp/trunk/rtl/verilog/
234	SBC Decimal mode 100% verified.	creep	5790d 17h	/t6507lp/trunk/rtl/verilog/
233	ADC and SBC are 100% verified in regular mode. Decimal mode still missing.	creep	5790d 21h	/t6507lp/trunk/rtl/verilog/
232	New video test.	creep	5792d 15h	/t6507lp/trunk/rtl/verilog/
231	Minor bugs fixed.	gabrieloshiro	5792d 17h	/t6507lp/trunk/rtl/verilog/
230	Changed TIA behavior. It is now pixel-based.	creep	5792d 17h	/t6507lp/trunk/rtl/verilog/
229	Created a one-line pattern.	creep	5792d 21h	/t6507lp/trunk/rtl/verilog/
228		gabrieloshiro	5792d 21h	/t6507lp/trunk/rtl/verilog/
227	Fixing conflicts.	creep	5792d 22h	/t6507lp/trunk/rtl/verilog/
226	work plz	creep	5792d 22h	/t6507lp/trunk/rtl/verilog/

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 253

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