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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 253

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Rev Log message Author Age Path
253 Changed the rw_mem signal name in the hierarchy creep 6118d 23h /t6507lp/trunk/rtl/verilog/
252 Added a stubs file for the pads. creep 6118d 23h /t6507lp/trunk/rtl/verilog/
251 Added the io wrapper creep 6119d 02h /t6507lp/trunk/rtl/verilog/
246 Added some older files plus the first syn script creep 6126d 02h /t6507lp/trunk/rtl/verilog/
243 Fixing STA_IDY bug creep 6167d 19h /t6507lp/trunk/rtl/verilog/
242 Bug regardind the STA_IDY opcode creep 6167d 22h /t6507lp/trunk/rtl/verilog/
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 6169d 00h /t6507lp/trunk/rtl/verilog/
238 ALU file is linted. creep 6171d 22h /t6507lp/trunk/rtl/verilog/
237 Added a preliminary collision detection logic. creep 6172d 23h /t6507lp/trunk/rtl/verilog/
236 Added the video converter testbench to the repository. creep 6173d 02h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 6173d 19h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 6178d 21h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 6179d 01h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 6180d 19h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 6180d 21h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 6180d 21h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 6181d 02h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 6181d 02h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 6181d 02h /t6507lp/trunk/rtl/verilog/
226 work plz creep 6181d 02h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 6181d 18h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 6181d 20h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 6181d 21h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 6181d 22h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 6182d 02h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 6182d 20h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 6185d 19h /t6507lp/trunk/rtl/verilog/
218 Added the video converter. creep 6185d 19h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 6187d 01h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 6187d 21h /t6507lp/trunk/rtl/verilog/

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