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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 253

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Rev Log message Author Age Path
253 Changed the rw_mem signal name in the hierarchy creep 5768d 14h /t6507lp/trunk/rtl/verilog/
252 Added a stubs file for the pads. creep 5768d 14h /t6507lp/trunk/rtl/verilog/
251 Added the io wrapper creep 5768d 17h /t6507lp/trunk/rtl/verilog/
246 Added some older files plus the first syn script creep 5775d 17h /t6507lp/trunk/rtl/verilog/
243 Fixing STA_IDY bug creep 5817d 10h /t6507lp/trunk/rtl/verilog/
242 Bug regardind the STA_IDY opcode creep 5817d 13h /t6507lp/trunk/rtl/verilog/
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 5818d 15h /t6507lp/trunk/rtl/verilog/
238 ALU file is linted. creep 5821d 12h /t6507lp/trunk/rtl/verilog/
237 Added a preliminary collision detection logic. creep 5822d 13h /t6507lp/trunk/rtl/verilog/
236 Added the video converter testbench to the repository. creep 5822d 17h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 5823d 10h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 5828d 12h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5828d 16h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 5830d 10h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 5830d 12h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 5830d 12h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 5830d 16h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 5830d 16h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 5830d 17h /t6507lp/trunk/rtl/verilog/
226 work plz creep 5830d 17h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 5831d 09h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 5831d 11h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5831d 11h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5831d 13h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5831d 16h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 5832d 11h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 5835d 09h /t6507lp/trunk/rtl/verilog/
218 Added the video converter. creep 5835d 10h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 5836d 16h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 5837d 12h /t6507lp/trunk/rtl/verilog/

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