OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 71

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5874d 22h /t6507lp/trunk/rtl/verilog/
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5878d 19h /t6507lp/trunk/rtl/verilog/
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5878d 21h /t6507lp/trunk/rtl/verilog/
67 File name change to lowercase. HAL says so! creep 5878d 23h /t6507lp/trunk/rtl/verilog/
66 File name change to lowercase. HAL says so! creep 5878d 23h /t6507lp/trunk/rtl/verilog/
65 Now the blocks are connected. gabrieloshiro 5879d 18h /t6507lp/trunk/rtl/verilog/
64 Constant were wrong. gabrieloshiro 5879d 18h /t6507lp/trunk/rtl/verilog/
63 Fixed several HAL warnings. Still plenty to do. creep 5879d 18h /t6507lp/trunk/rtl/verilog/
62 The DUT file name changed. creep 5879d 18h /t6507lp/trunk/rtl/verilog/
61 File name change to lowercase. HAL says so! creep 5879d 18h /t6507lp/trunk/rtl/verilog/
60 File name change. HAL says so! creep 5879d 19h /t6507lp/trunk/rtl/verilog/
59 I`ve fixed some latch creation. gabrieloshiro 5879d 19h /t6507lp/trunk/rtl/verilog/
58 ALU with all opcodes ready for simulation. gabrieloshiro 5879d 19h /t6507lp/trunk/rtl/verilog/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5879d 19h /t6507lp/trunk/rtl/verilog/
56 Several changes in the output logic to respect the pipelining. creep 5879d 19h /t6507lp/trunk/rtl/verilog/
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5879d 20h /t6507lp/trunk/rtl/verilog/
54 Processor Status register modified. gabrieloshiro 5879d 23h /t6507lp/trunk/rtl/verilog/
53 Added default header. creep 5880d 03h /t6507lp/trunk/rtl/verilog/
52 Removed unecessary always block. creep 5880d 19h /t6507lp/trunk/rtl/verilog/
51 Some first ideas on testbench. creep 5880d 19h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.