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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 92

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Rev Log message Author Age Path
92 Absolute indexed mode working properly. All cases were simulated. creep 5847d 17h /t6507lp/trunk/rtl/verilog/
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5847d 17h /t6507lp/trunk/rtl/verilog/
90 CMP, CPX and CPY affect carry flag (in this case it indicates a borrow) but they don't affect overflow. gabrieloshiro 5847d 17h /t6507lp/trunk/rtl/verilog/
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5847d 18h /t6507lp/trunk/rtl/verilog/
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5847d 18h /t6507lp/trunk/rtl/verilog/
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5848d 10h /t6507lp/trunk/rtl/verilog/
86 Zero page indexed mode is working fine. creep 5848d 13h /t6507lp/trunk/rtl/verilog/
85 alu_x and alu_y variables created. gabrieloshiro 5848d 18h /t6507lp/trunk/rtl/verilog/
84 X and Y register are passed from ALU to FSM. gabrieloshiro 5848d 18h /t6507lp/trunk/rtl/verilog/
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5848d 18h /t6507lp/trunk/rtl/verilog/
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5849d 10h /t6507lp/trunk/rtl/verilog/
81 Decimal mode (BCD) is working. gabrieloshiro 5849d 11h /t6507lp/trunk/rtl/verilog/
80 Grouping some instructions that have the same behavioral. gabrieloshiro 5849d 11h /t6507lp/trunk/rtl/verilog/
79 ALU testbench added. gabrieloshiro 5849d 12h /t6507lp/trunk/rtl/verilog/
78 ZPG coded and simulated. creep 5849d 12h /t6507lp/trunk/rtl/verilog/
77 ZPG coded. Simulation is halfway. creep 5849d 13h /t6507lp/trunk/rtl/verilog/
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5849d 13h /t6507lp/trunk/rtl/verilog/
75 First working version! gabrieloshiro 5849d 13h /t6507lp/trunk/rtl/verilog/
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5849d 14h /t6507lp/trunk/rtl/verilog/
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5853d 10h /t6507lp/trunk/rtl/verilog/

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