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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp.v] - Rev 255

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Rev Log message Author Age Path
251 Added the io wrapper creep 5621d 10h /t6507lp/trunk/rtl/verilog/t6507lp.v
187 Fixed the module name. creep 5710d 02h /t6507lp/trunk/rtl/verilog/t6507lp.v
136 Some minor coding style changes. gabrieloshiro 5726d 06h /t6507lp/trunk/rtl/verilog/t6507lp.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5730d 09h /t6507lp/trunk/rtl/verilog/t6507lp.v
118 The top level name was in uppercase. The correct is lowercase. creep 5732d 10h /t6507lp/trunk/rtl/verilog/t6507lp.v

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