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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 172

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Rev Log message Author Age Path
172 RTI supported to be compatible with stella gabrieloshiro 5717d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
171 Removed debug messages. creep 5717d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
169 ADC bugs finally fixed. gabrieloshiro 5718d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5718d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
167 Now SBC is supposed to work. gabrieloshiro 5718d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
166 Commiting again! gabrieloshiro 5718d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
165 SBC and PHP fixed! gabrieloshiro 5718d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5718d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5718d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5718d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5718d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5721d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
157 gabrieloshiro 5721d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5721d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.
gabrieloshiro 5721d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
152 Bug #24 from trac was fixed. gabrieloshiro 5722d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151 tah comitado! gabrieloshiro 5722d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5722d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5722d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5722d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

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