OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 174

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
174 SBC borrow flag bug fixed... again gabrieloshiro 5726d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5726d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
172 RTI supported to be compatible with stella gabrieloshiro 5726d 10h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
171 Removed debug messages. creep 5726d 10h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
169 ADC bugs finally fixed. gabrieloshiro 5727d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5727d 04h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
167 Now SBC is supposed to work. gabrieloshiro 5727d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
166 Commiting again! gabrieloshiro 5727d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
165 SBC and PHP fixed! gabrieloshiro 5727d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5727d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5727d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5727d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5727d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5730d 04h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
157 gabrieloshiro 5730d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5730d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.
gabrieloshiro 5730d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
152 Bug #24 from trac was fixed. gabrieloshiro 5731d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151 tah comitado! gabrieloshiro 5731d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5731d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.