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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 183

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183 STA, STY and STX should be working now gabrieloshiro 5725d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5725d 21h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
179 STA, STY and STX fixed gabrieloshiro 5726d 00h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
178 STA, STY and STX fixed gabrieloshiro 5726d 00h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
176 RTI works for me gabrieloshiro 5726d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5726d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5726d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5726d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
172 RTI supported to be compatible with stella gabrieloshiro 5727d 01h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
171 Removed debug messages. creep 5727d 02h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
169 ADC bugs finally fixed. gabrieloshiro 5727d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5727d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
167 Now SBC is supposed to work. gabrieloshiro 5727d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
166 Commiting again! gabrieloshiro 5727d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
165 SBC and PHP fixed! gabrieloshiro 5727d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5727d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5727d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5727d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5727d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5730d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

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