URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 214

Rev	Log message	Author	Age	Path
161	Sum and subtract were wrong when D flag was HIGH.	gabrieloshiro	6098d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158	Bug 28 fixed. PHA was not coping the register to alu_a output	gabrieloshiro	6101d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
157		gabrieloshiro	6101d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
156	Some bugs were fixed. Testbench were expecting wrong values sometimes.	gabrieloshiro	6101d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
154	BRK_IMP was asserting 0 to B flag. Bug report #25 fixed.	gabrieloshiro	6101d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
152	Bug #24 from trac was fixed.	gabrieloshiro	6102d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151	tah comitado!	gabrieloshiro	6102d 04h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	6102d 04h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
149	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	6102d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
148	Reset assertion was commented. It was not working properly.	gabrieloshiro	6102d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v