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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Rev 255

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224 Added a top level for the tests. creep 5684d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
186 Testbench has a lot of new tests. gabrieloshiro 5717d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5717d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
183 STA, STY and STX should be working now gabrieloshiro 5718d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5718d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
179 STA, STY and STX fixed gabrieloshiro 5718d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
178 STA, STY and STX fixed gabrieloshiro 5718d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
176 RTI works for me gabrieloshiro 5718d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5719d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5719d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
169 ADC bugs finally fixed. gabrieloshiro 5720d 04h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
165 SBC and PHP fixed! gabrieloshiro 5720d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5720d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5720d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5723d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5723d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5724d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5724d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5724d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5725d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v

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