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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 211

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205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 6230d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
202 Bug #49: RTI and RTS behavior was recoded. creep 6233d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
200 Bug #48: SP wrong after decrement. creep 6233d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
199 Fixed two warning messages at the FSM. creep 6233d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
196 Syncing both repositories. creep 6234d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
195 FSM was locking on TSX/TXS. creep 6234d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
194 Fixing bug #45 creep 6234d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
146 Fixed ticket #13: reset behavior in the FSM. creep 6256d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 6261d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 6263d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 6263d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 6263d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 6263d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 6264d 07h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 6264d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109 PLA and PLP are coded and simulated. creep 6264d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108 PHA and PHP are coded and simulated. creep 6264d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 6264d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 6264d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 6264d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 6265d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 6265d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 6265d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 6265d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 6268d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 6268d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 6269d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 6269d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 6270d 07h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86 Zero page indexed mode is working fine. creep 6270d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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