URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 223

Rev	Log message	Author	Age	Path
104	The BRK instruction is working. The reset vector was tested also.	creep	5838d 13h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103	Some early modifications to support the special stack instructions.	creep	5839d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102	Some early modifications to support the special stack instructions.	creep	5839d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101	Absolute indirect addressing mode is coded and simulated.	creep	5839d 13h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5839d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96	IDY READ TYPE instructions are coded and simulated. IDY WRITE TYPE instructions are coded but still requires simulation.	creep	5842d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95	IDX addressing mode is also 100%, coded and simulated.	creep	5842d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94	Relative addressing mode is almost 100% functional. It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.	creep	5843d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88	Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated.	creep	5843d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87	Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated.	creep	5844d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v