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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 230

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212 Bug #56: ZPX page crossing. creep 5699d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5702d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
202 Bug #49: RTI and RTS behavior was recoded. creep 5705d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
200 Bug #48: SP wrong after decrement. creep 5705d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
199 Fixed two warning messages at the FSM. creep 5705d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
196 Syncing both repositories. creep 5706d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
195 FSM was locking on TSX/TXS. creep 5706d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
194 Fixing bug #45 creep 5706d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
146 Fixed ticket #13: reset behavior in the FSM. creep 5728d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5733d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 5735d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 5735d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 5735d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 5735d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 5736d 10h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5736d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109 PLA and PLP are coded and simulated. creep 5736d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108 PHA and PHP are coded and simulated. creep 5736d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 5736d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 5736d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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