URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 253

Rev	Log message	Author	Age	Path
109	PLA and PLP are coded and simulated.	creep	5876d 01h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108	PHA and PHP are coded and simulated.	creep	5876d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107	The RTS instruction is working fine. Coded and simulated.	creep	5876d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105	The RTI instruction is working fine. Coded and simulated.	creep	5876d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104	The BRK instruction is working. The reset vector was tested also.	creep	5876d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103	Some early modifications to support the special stack instructions.	creep	5876d 23h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102	Some early modifications to support the special stack instructions.	creep	5877d 01h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101	Absolute indirect addressing mode is coded and simulated.	creep	5877d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5877d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96	IDY READ TYPE instructions are coded and simulated. IDY WRITE TYPE instructions are coded but still requires simulation.	creep	5879d 22h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v