OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Rev 96

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5851d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5851d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5852d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
92 Absolute indexed mode working properly. All cases were simulated. creep 5852d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5852d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5852d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5852d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5853d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
86 Zero page indexed mode is working fine. creep 5853d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
78 ZPG coded and simulated. creep 5854d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5854d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5854d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5858d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
67 File name change to lowercase. HAL says so! creep 5858d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.