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Rev Log message Author Age Path
113 Timescale was unified. gabrieloshiro 5567d 23h /
112 Created a global timescale file for the project. creep 5567d 23h /
111 Performed some linting after coding was finished. creep 5568d 15h /
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5568d 16h /
109 PLA and PLP are coded and simulated. creep 5568d 18h /
108 PHA and PHP are coded and simulated. creep 5568d 19h /
107 The RTS instruction is working fine. Coded and simulated. creep 5568d 20h /
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5568d 20h /
105 The RTI instruction is working fine. Coded and simulated. creep 5568d 20h /
104 The BRK instruction is working. The reset vector was tested also. creep 5568d 22h /
103 Some early modifications to support the special stack instructions. creep 5569d 16h /
102 Some early modifications to support the special stack instructions. creep 5569d 19h /
101 Absolute indirect addressing mode is coded and simulated. creep 5569d 22h /
100 IDY WRITE TYPE instructions are coded and simulated. creep 5569d 23h /
99 Only Package.v should be used. creep 5570d 00h /
98 Updated status and some comments. creep 5570d 00h /
97 Removed obsolete TODO. creep 5570d 00h /
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.
creep 5572d 15h /
95 IDX addressing mode is also 100%, coded and simulated. creep 5572d 19h /
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.
creep 5573d 15h /

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