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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev Log message Author Age Path
262 Final synthesis script. creep 5581d 19h /
261 Added a better clock gating scheme with enable sharing creep 5581d 22h /
260 removing useless files creep 5584d 16h /
259 sync creep 5584d 16h /
258 Fixed the input parametric testing logic, removed a pad. creep 5584d 16h /
257 Modified script for DFT creep 5606d 19h /
256 fp files creep 5606d 19h /
255 Changed the PADS verilog description to minimize violations creep 5606d 19h /
254 Fixed a latch in the design creep 5606d 19h /
253 Changed the rw_mem signal name in the hierarchy creep 5629d 20h /
252 Added a stubs file for the pads. creep 5629d 20h /
251 Added the io wrapper creep 5629d 23h /
250 Synthesis script changed creep 5629d 23h /
249 Renamed the synthesis script creep 5630d 19h /
248 Added a low power synthesis script creep 5635d 18h /
247 Added the cpu mapped verilog creep 5635d 18h /
246 Added some older files plus the first syn script creep 5636d 22h /
245 Added a few dirs for the synthesis creep 5636d 22h /
244 Added a few dirs for the synthesis creep 5636d 23h /
243 Fixing STA_IDY bug creep 5678d 15h /
242 Bug regardind the STA_IDY opcode creep 5678d 19h /
241 Fixed half the problem with strange STA behavior. creep 5679d 18h /
240 Finally fixed the decimal mode! creep 5679d 20h /
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 5679d 21h /
238 ALU file is linted. creep 5682d 18h /
237 Added a preliminary collision detection logic. creep 5683d 19h /
236 Added the video converter testbench to the repository. creep 5683d 22h /
235 Bug #60: added a brief simulation to the video_converter module. creep 5684d 16h /
234 SBC Decimal mode 100% verified. creep 5689d 18h /
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5689d 22h /

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