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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev Log message Author Age Path
262 Final synthesis script. creep 5915d 22h /
261 Added a better clock gating scheme with enable sharing creep 5916d 00h /
260 removing useless files creep 5918d 19h /
259 sync creep 5918d 19h /
258 Fixed the input parametric testing logic, removed a pad. creep 5918d 19h /
257 Modified script for DFT creep 5940d 21h /
256 fp files creep 5940d 22h /
255 Changed the PADS verilog description to minimize violations creep 5940d 22h /
254 Fixed a latch in the design creep 5940d 22h /
253 Changed the rw_mem signal name in the hierarchy creep 5963d 22h /
252 Added a stubs file for the pads. creep 5963d 22h /
251 Added the io wrapper creep 5964d 01h /
250 Synthesis script changed creep 5964d 02h /
249 Renamed the synthesis script creep 5964d 22h /
248 Added a low power synthesis script creep 5969d 20h /
247 Added the cpu mapped verilog creep 5969d 20h /
246 Added some older files plus the first syn script creep 5971d 01h /
245 Added a few dirs for the synthesis creep 5971d 01h /
244 Added a few dirs for the synthesis creep 5971d 01h /
243 Fixing STA_IDY bug creep 6012d 18h /
242 Bug regardind the STA_IDY opcode creep 6012d 22h /
241 Fixed half the problem with strange STA behavior. creep 6013d 20h /
240 Finally fixed the decimal mode! creep 6013d 23h /
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 6013d 23h /
238 ALU file is linted. creep 6016d 21h /
237 Added a preliminary collision detection logic. creep 6017d 22h /
236 Added the video converter testbench to the repository. creep 6018d 01h /
235 Bug #60: added a brief simulation to the video_converter module. creep 6018d 19h /
234 SBC Decimal mode 100% verified. creep 6023d 20h /
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 6024d 00h /

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