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Rev Log message Author Age Path
25 UART16750: Updated testbench hasw 5245d 13h /
24 Inverted low active outputs when RST is active hasw 5245d 14h /
23 Fixed paths in Makefile for simulation hasw 5609d 16h /
22 Removed old stimuli data file, created by perl script hasw 5609d 16h /
21 Updated simulation files hasw 5609d 17h /
20 UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state hasw 5739d 15h /
19 Added old uploaded documents to new repository. root 5755d 19h /
18 Added old uploaded documents to new repository. root 5756d 00h /
17 New directory structure. root 5756d 00h /
16 UART16750: Added example project hasw 5776d 12h /
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5785d 14h /
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5786d 16h /
13 UART16750: Added automatic flow control hasw 5799d 17h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5799d 17h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5799d 17h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5799d 18h /
9 Registered control line outputs hasw 5808d 19h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5808d 19h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5810d 00h /
6 THR empty interrupt register connected to RST hasw 5810d 00h /
5 Removed old component hasw 5810d 19h /
4 Removed swap file hasw 5810d 20h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5810d 20h /
2 Imported sources hasw 5810d 20h /
1 Standard project directories initialized by cvs2svn. 5810d 20h /

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