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URL https://opencores.org/ocsvn/usb11/usb11/trunk

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[/] [usb11/] [trunk] - Rev 13

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Rev Log message Author Age Path
13 New directory structure. root 5756d 19h /usb11/trunk
12 Correction of the out2, out4 and out6 function DATA MISMATCH ERROR message. alfoltran 7503d 06h /trunk
11 Correction of the out2, out4 and out6 function DATA MISMATCH ERROR message.
Modification in out4 and out6 functions for XILINX TIMED SIMULATION.
alfoltran 7503d 06h /trunk
10 All project files in ZIP. alfoltran 7503d 06h /trunk
9 All project files in one ZIP file. alfoltran 7517d 13h /trunk
8 Verilog defines file for testbench. alfoltran 7517d 13h /trunk
7 All files in '.zip'. alfoltran 7520d 10h /trunk
6 Task in5 correction: no ACK for length zero packet. alfoltran 7520d 10h /trunk
5 Function in5 correction: no ACK for length zero packet. alfoltran 7520d 10h /trunk
4 USB1.1 Testbench Documentation alfoltran 7520d 10h /trunk
3 All projects files in '.zip'. alfoltran 7521d 10h /trunk
2 Initial version in OpenCores.org (2004/04/10 - 19:22GMT) alfoltran 7521d 10h /trunk
1 Standard project directories initialized by cvs2svn. 7521d 10h /trunk

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