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[/] [a-z80/] [trunk/] [cpu/] [control/] [simulation/] [modelsim/] - Rev 8

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Last modification

  • Rev 8, 2016-03-12 19:27:53 GMT
  • Author: gdevic
  • Log message:
    z80: Release 4
Path
/a-z80/trunk/cpu/alu/alu_flags.bdf
/a-z80/trunk/cpu/alu/alu_flags.bsf
/a-z80/trunk/cpu/alu/alu_flags.v
/a-z80/trunk/cpu/alu/simulation/modelsim/test_alu.mpf
/a-z80/trunk/cpu/bus/address_latch.bdf
/a-z80/trunk/cpu/bus/address_latch.bsf
/a-z80/trunk/cpu/bus/address_latch.v
/a-z80/trunk/cpu/bus/bus_control.bdf
/a-z80/trunk/cpu/bus/bus_control.bsf
/a-z80/trunk/cpu/bus/bus_control.v
/a-z80/trunk/cpu/bus/bus_switch.sv
/a-z80/trunk/cpu/bus/bus_switch.v
/a-z80/trunk/cpu/bus/data_pins.bdf
/a-z80/trunk/cpu/bus/data_pins.bsf
/a-z80/trunk/cpu/bus/data_pins.v
/a-z80/trunk/cpu/bus/simulation/modelsim/test_bus.mpf
/a-z80/trunk/cpu/bus/simulation/modelsim/wave_bus.do
/a-z80/trunk/cpu/bus/test_bus.qsf
/a-z80/trunk/cpu/bus/test_bus.sv
/a-z80/trunk/cpu/bus/test_pins.sv
/a-z80/trunk/cpu/control/clk_delay.bdf
/a-z80/trunk/cpu/control/execute.bsf
/a-z80/trunk/cpu/control/execute.sv
/a-z80/trunk/cpu/control/execute.v
/a-z80/trunk/cpu/control/exec_matrix.vh
/a-z80/trunk/cpu/control/exec_matrix_compiled.vh
/a-z80/trunk/cpu/control/exec_module.vh
/a-z80/trunk/cpu/control/exec_zero.vh
/a-z80/trunk/cpu/control/gencompile.py
/a-z80/trunk/cpu/control/genmatrix.py
/a-z80/trunk/cpu/control/genref.py
/a-z80/trunk/cpu/control/interrupts.bdf
/a-z80/trunk/cpu/control/interrupts.bsf
/a-z80/trunk/cpu/control/interrupts.v
/a-z80/trunk/cpu/control/ir.bdf
/a-z80/trunk/cpu/control/ir.bsf
/a-z80/trunk/cpu/control/ir.v
/a-z80/trunk/cpu/control/pla_decode.sv
/a-z80/trunk/cpu/control/pla_decode.v
/a-z80/trunk/cpu/control/resets.bdf
/a-z80/trunk/cpu/control/resets.v
/a-z80/trunk/cpu/control/sequencer.bdf
/a-z80/trunk/cpu/control/sequencer.bsf
/a-z80/trunk/cpu/control/sequencer.v
/a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf
/a-z80/trunk/cpu/control/simulation/modelsim/wave_sequencer.do
/a-z80/trunk/cpu/control/temp_wires.vh
/a-z80/trunk/cpu/control/test_control.qsf
/a-z80/trunk/cpu/control/test_decode.sv
/a-z80/trunk/cpu/control/test_interrupts.sv
/a-z80/trunk/cpu/control/test_reset.sv
/a-z80/trunk/cpu/control/test_sequencer.sv
/a-z80/trunk/cpu/control/Timings.csv
/a-z80/trunk/cpu/control/Timings.xlsm
/a-z80/trunk/cpu/control/timing_macros.i
/a-z80/trunk/cpu/copyleft.txt
/a-z80/trunk/cpu/deploy
/a-z80/trunk/cpu/export.py
/a-z80/trunk/cpu/registers/reg_control.bdf
/a-z80/trunk/cpu/registers/reg_control.bsf
/a-z80/trunk/cpu/registers/reg_control.v
/a-z80/trunk/cpu/registers/reg_file.bdf
/a-z80/trunk/cpu/registers/reg_file.bsf
/a-z80/trunk/cpu/registers/reg_file.v
/a-z80/trunk/cpu/registers/simulation/modelsim/test_registers.mpf
/a-z80/trunk/cpu/registers/simulation/modelsim/wave_registers.do
/a-z80/trunk/cpu/registers/test_regfile.sv
/a-z80/trunk/cpu/registers/test_registers.sv
/a-z80/trunk/cpu/top-level-files.txt
/a-z80/trunk/cpu/toplevel/core.vh
/a-z80/trunk/cpu/toplevel/coremodules.vh
/a-z80/trunk/cpu/toplevel/gencoremodules.py
/a-z80/trunk/cpu/toplevel/genfuse.py
/a-z80/trunk/cpu/toplevel/genglobals.py
/a-z80/trunk/cpu/toplevel/globals.vh
/a-z80/trunk/cpu/toplevel/simulation/modelsim/test_top.mpf
/a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do
/a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_top.do
/a-z80/trunk/cpu/toplevel/test_fuse.vh
/a-z80/trunk/cpu/toplevel/test_top.sv
/a-z80/trunk/cpu/toplevel/toplevel.bdf
/a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv
/a-z80/trunk/cpu/toplevel/z80_top_direct_n.v
/a-z80/trunk/docs/A-Z80_UsersGuide.docx
/a-z80/trunk/docs/A-Z80_UsersGuide.pdf
/a-z80/trunk/docs/pdf
/a-z80/trunk/docs/pdf/a-z80-toplevel.pdf
/a-z80/trunk/docs/pdf/address_latch.pdf
/a-z80/trunk/docs/pdf/address_mux.pdf
/a-z80/trunk/docs/pdf/address_pins.pdf
/a-z80/trunk/docs/pdf/alu.pdf
/a-z80/trunk/docs/pdf/alu_bit_select.pdf
/a-z80/trunk/docs/pdf/alu_control.pdf
/a-z80/trunk/docs/pdf/alu_core.pdf
/a-z80/trunk/docs/pdf/alu_flags.pdf
/a-z80/trunk/docs/pdf/alu_mux_2.pdf
/a-z80/trunk/docs/pdf/alu_mux_2z.pdf
/a-z80/trunk/docs/pdf/alu_mux_3z.pdf
/a-z80/trunk/docs/pdf/alu_mux_4.pdf
/a-z80/trunk/docs/pdf/alu_mux_8.pdf
/a-z80/trunk/docs/pdf/alu_prep_daa.pdf
/a-z80/trunk/docs/pdf/alu_select.pdf
/a-z80/trunk/docs/pdf/alu_shifter_core.pdf
/a-z80/trunk/docs/pdf/alu_slice.pdf
/a-z80/trunk/docs/pdf/bus_control.pdf
/a-z80/trunk/docs/pdf/clk_delay.pdf
/a-z80/trunk/docs/pdf/control_pins_n.pdf
/a-z80/trunk/docs/pdf/data_pins.pdf
/a-z80/trunk/docs/pdf/data_switch.pdf
/a-z80/trunk/docs/pdf/data_switch_mask.pdf
/a-z80/trunk/docs/pdf/decode_state.pdf
/a-z80/trunk/docs/pdf/inc_dec.pdf
/a-z80/trunk/docs/pdf/inc_dec_2bit.pdf
/a-z80/trunk/docs/pdf/interrupts.pdf
/a-z80/trunk/docs/pdf/ir.pdf
/a-z80/trunk/docs/pdf/memory_ifc.pdf
/a-z80/trunk/docs/pdf/pin_control.pdf
/a-z80/trunk/docs/pdf/reg_control.pdf
/a-z80/trunk/docs/pdf/reg_file.pdf
/a-z80/trunk/docs/pdf/reg_latch.pdf
/a-z80/trunk/docs/pdf/resets.pdf
/a-z80/trunk/docs/pdf/sequencer.pdf
/a-z80/trunk/docs/png/z80-address_latch.png
/a-z80/trunk/docs/png/z80-address_mux.png
/a-z80/trunk/docs/png/z80-address_pins.png
/a-z80/trunk/docs/png/z80-alu.png
/a-z80/trunk/docs/png/z80-alu_bit_select.png
/a-z80/trunk/docs/png/z80-alu_control.png
/a-z80/trunk/docs/png/z80-alu_core.png
/a-z80/trunk/docs/png/z80-alu_flags.png
/a-z80/trunk/docs/png/z80-alu_mux_2.png
/a-z80/trunk/docs/png/z80-alu_mux_2z.png
/a-z80/trunk/docs/png/z80-alu_mux_3z.png
/a-z80/trunk/docs/png/z80-alu_mux_4.png
/a-z80/trunk/docs/png/z80-alu_mux_8.png
/a-z80/trunk/docs/png/z80-alu_prep_daa.png
/a-z80/trunk/docs/png/z80-alu_select.png
/a-z80/trunk/docs/png/z80-alu_shifter_core.png
/a-z80/trunk/docs/png/z80-alu_slice.png
/a-z80/trunk/docs/png/z80-bus_control.png
/a-z80/trunk/docs/png/z80-clk_delay.png
/a-z80/trunk/docs/png/z80-control_pins_n.png
/a-z80/trunk/docs/png/z80-data_pins.png
/a-z80/trunk/docs/png/z80-data_switch.png
/a-z80/trunk/docs/png/z80-data_switch_mask.png
/a-z80/trunk/docs/png/z80-decode_state.png
/a-z80/trunk/docs/png/z80-inc_dec.png
/a-z80/trunk/docs/png/z80-inc_dec_2bit.png
/a-z80/trunk/docs/png/z80-interrupts.png
/a-z80/trunk/docs/png/z80-ir.png
/a-z80/trunk/docs/png/z80-memory_ifc.png
/a-z80/trunk/docs/png/z80-pin_control.png
/a-z80/trunk/docs/png/z80-reg_control.png
/a-z80/trunk/docs/png/z80-reg_file.png
/a-z80/trunk/docs/png/z80-reg_latch.png
/a-z80/trunk/docs/png/z80-resets.png
/a-z80/trunk/docs/png/z80-sequencer.png
/a-z80/trunk/docs/QuickStart.docx
/a-z80/trunk/docs/QuickStart.pdf
/a-z80/trunk/docs/xps
/a-z80/trunk/host/basic
/a-z80/trunk/host/basic_de1
/a-z80/trunk/host/basic_de1/basic_de1.qpf
/a-z80/trunk/host/basic_de1/basic_de1.qsf
/a-z80/trunk/host/basic_de1/basic_de1.sdc
/a-z80/trunk/host/basic_de1/basic_de1_fpga.sv
/a-z80/trunk/host/basic_de1/basic_de1_ModelSim.sv
/a-z80/trunk/host/basic_de1/fpga.hex
/a-z80/trunk/host/basic_de1/pll.ppf
/a-z80/trunk/host/basic_de1/pll.qip
/a-z80/trunk/host/basic_de1/pll.v
/a-z80/trunk/host/basic_de1/ram.qip
/a-z80/trunk/host/basic_de1/ram.v
/a-z80/trunk/host/basic_de1/readme.txt
/a-z80/trunk/host/basic_de1/simulation
/a-z80/trunk/host/basic_de1/simulation/modelsim
/a-z80/trunk/host/basic_de1/simulation/modelsim/fpga.hex
/a-z80/trunk/host/basic_de1/simulation/modelsim/r
/a-z80/trunk/host/basic_de1/simulation/modelsim/test_host.mpf
/a-z80/trunk/host/basic_de1/simulation/modelsim/wave_host.do
/a-z80/trunk/host/basic_de1/test_host.sv
/a-z80/trunk/host/basic_nexys3
/a-z80/trunk/host/basic_nexys3/basic_nexys3.xise
/a-z80/trunk/host/basic_nexys3/basic_nexys3_fpga.v
/a-z80/trunk/host/basic_nexys3/cscope.cdc
/a-z80/trunk/host/basic_nexys3/ipcore_dir
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.asy
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.gise
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.ucf
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.v
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.veo
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xco
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xise
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.ucf
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.v
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.xdc
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/implement.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/implement.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/xst.prj
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/xst.scr
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/clock_tb.v
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simcmds.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.do
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_ncsim.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_vcs.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/ucli_commands.key
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/vcs_session.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.do
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.sv
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/clock_tb.v
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/sdf_cmd_file
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simcmds.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_isim.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.bat
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.do
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_ncsim.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_vcs.sh
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/ucli_commands.key
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/vcs_session.tcl
/a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/wave.do
/a-z80/trunk/host/basic_nexys3/ipcore_dir/coregen.cgp
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.asy
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.cdc
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints/ila.ucf
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints/ila.xdc
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.gise
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ncf
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ngc
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.sym
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ucf
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.v
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.veo
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xco
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xdc
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xise
/a-z80/trunk/host/basic_nexys3/ipcore_dir/ila_xmdf.tcl
/a-z80/trunk/host/basic_nexys3/Nexys3_master.ucf
/a-z80/trunk/host/basic_nexys3/ram.v
/a-z80/trunk/host/basic_nexys3/readme.txt
/a-z80/trunk/host/basic_nexys3/test_host.v
/a-z80/trunk/host/basic_nexys3/work
/a-z80/trunk/host/basic_nexys3/work/ram.mif
/a-z80/trunk/host/common
/a-z80/trunk/host/common/uart.v
/a-z80/trunk/host/zxspectrum
/a-z80/trunk/host/zxspectrum_de1
/a-z80/trunk/host/zxspectrum_de1/pll.ppf
/a-z80/trunk/host/zxspectrum_de1/pll.qip
/a-z80/trunk/host/zxspectrum_de1/pll.v
/a-z80/trunk/host/zxspectrum_de1/ram16.qip
/a-z80/trunk/host/zxspectrum_de1/ram16.v
/a-z80/trunk/host/zxspectrum_de1/readme.txt
/a-z80/trunk/host/zxspectrum_de1/rom
/a-z80/trunk/host/zxspectrum_de1/rom/assemble.bat
/a-z80/trunk/host/zxspectrum_de1/rom/combined.rom
/a-z80/trunk/host/zxspectrum_de1/rom/gw03.rom
/a-z80/trunk/host/zxspectrum_de1/rom/readme.txt
/a-z80/trunk/host/zxspectrum_de1/rom/tasm.exe
/a-z80/trunk/host/zxspectrum_de1/rom/tasm80.tab
/a-z80/trunk/host/zxspectrum_de1/rom/zxspectrum_rom.asm
/a-z80/trunk/host/zxspectrum_de1/ula
/a-z80/trunk/host/zxspectrum_de1/ula/clocks.sv
/a-z80/trunk/host/zxspectrum_de1/ula/i2c_loader.vhd
/a-z80/trunk/host/zxspectrum_de1/ula/i2s_intf.vhd
/a-z80/trunk/host/zxspectrum_de1/ula/pll.ppf
/a-z80/trunk/host/zxspectrum_de1/ula/pll.qip
/a-z80/trunk/host/zxspectrum_de1/ula/pll.v
/a-z80/trunk/host/zxspectrum_de1/ula/ps2_kbd.sv
/a-z80/trunk/host/zxspectrum_de1/ula/ram8.qip
/a-z80/trunk/host/zxspectrum_de1/ula/ram8.v
/a-z80/trunk/host/zxspectrum_de1/ula/test_scr.hex
/a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qpf
/a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qsf
/a-z80/trunk/host/zxspectrum_de1/ula/test_ula.sv
/a-z80/trunk/host/zxspectrum_de1/ula/ula.sv
/a-z80/trunk/host/zxspectrum_de1/ula/video.sv
/a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv
/a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qpf
/a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qsf
/a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv
/a-z80/trunk/modelsim_pre_commit.py
/a-z80/trunk/modelsim_setup.py
/a-z80/trunk/readme.txt
/a-z80/trunk/resources/connotate-fuse.bat
/a-z80/trunk/resources/connotate-fuse.py
/a-z80/trunk/resources/process-pla.py
/a-z80/trunk/tools/dongle/daa/simulate-daa.py
/a-z80/trunk/tools/dongle/daa/z80-instruction-test-daa.py
/a-z80/trunk/tools/dongle/neg/simulate-neg.py
/a-z80/trunk/tools/dongle/sbc/simulate-sbc.py
/a-z80/trunk/tools/dongle/sbc/simulate-sub.py
/a-z80/trunk/tools/readme.txt
/a-z80/trunk/tools/z80_pla_checker/source/ClassPLA.cs
/a-z80/trunk/tools/z80_pla_checker/z80_pla_checker.exe
/a-z80/trunk/tools/zmac/bin2coe.py
/a-z80/trunk/tools/zmac/bin2mif.py
/a-z80/trunk/tools/zmac/bindump.py
/a-z80/trunk/tools/zmac/fpga.hex
/a-z80/trunk/tools/zmac/hello_world.asm
/a-z80/trunk/tools/zmac/make_fpga.bat

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