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        <title>a-z80</title>
        <description>WebSVN RSS feed - a-z80</description>
        <link>https://lists.opencores.org/websvn//websvn/listing?repname=a-z80&amp;path=%2Fa-z80%2F&amp;</link>
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        <item>
            <title>Documentation update</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=22</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 22 - gdevic&lt;/strong&gt; (9 file(s) modified)&lt;/div&gt;&lt;div&gt;Documentation update&lt;/div&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.docx&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.pdf&lt;br /&gt;~ /a-z80/trunk/readme.txt&lt;br /&gt;~ /a-z80/trunk/resources/process-pla.py&lt;br /&gt;~ /a-z80/trunk/tools/readme.txt&lt;br /&gt;~ /a-z80/trunk/tools/z80_pla_checker/readme.txt&lt;br /&gt;~ /a-z80/trunk/tools/zmac/readme.txt&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sun, 12 Jul 2020 16:35:29 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=22</guid>
        </item>
        <item>
            <title>Update zmac assembler to version 5jan2019</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=21</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 21 - gdevic&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Update zmac assembler to version 5jan2019&lt;/div&gt;~ /a-z80/trunk/tools/zmac/zmac.exe&lt;br /&gt;~ /a-z80/trunk/tools/zmac/zmac.html&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Tue, 05 May 2020 15:23:51 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=21</guid>
        </item>
        <item>
            <title>Revert &amp;quot;Corrected unconnected enable line&amp;quot; in memory_ifc module. ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=20</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 20 - gdevic&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Revert &amp;quot;Corrected unconnected enable line&amp;quot; in memory_ifc module. Fixes erroneous ...&lt;/div&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.v&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Mon, 10 Dec 2018 01:19:18 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=20</guid>
        </item>
        <item>
            <title>Some documentation updates</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=19</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 19 - gdevic&lt;/strong&gt; (7 file(s) modified)&lt;/div&gt;&lt;div&gt;Some documentation updates&lt;/div&gt;~ /a-z80/trunk/cpu/export.py&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.docx&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.pdf&lt;br /&gt;~ /a-z80/trunk/readme.txt&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Wed, 28 Nov 2018 20:55:30 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=19</guid>
        </item>
        <item>
            <title>Correctly latch IO RW wait request
    
Fixed ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=18</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 18 - gdevic&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;Correctly latch IO RW wait request&lt;br /&gt;
    &lt;br /&gt;
Fixed ...&lt;/div&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.v&lt;br /&gt;+ /a-z80/trunk/cpu/readme.txt&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;~ /a-z80/trunk/readme.txt&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 24 Feb 2018 06:48:20 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=18</guid>
        </item>
        <item>
            <title>z80: Release 5</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=17</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 17 - gdevic&lt;/strong&gt; (10 file(s) modified)&lt;/div&gt;&lt;div&gt;z80: Release 5&lt;/div&gt;~ /a-z80/trunk/cpu/bus/data_pins_lattice.v&lt;br /&gt;~ /a-z80/trunk/cpu/export.py&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.docx&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.pdf&lt;br /&gt;~ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xise&lt;br /&gt;~ /a-z80/trunk/host/common/uart.v&lt;br /&gt;~ /a-z80/trunk/readme.txt&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Thu, 12 Jan 2017 07:02:24 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=17</guid>
        </item>
        <item>
            <title>Simplify by adding nhold_clk_wait

Inverted version is used to feel AND ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=16</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 16 - gdevic&lt;/strong&gt; (26 file(s) modified)&lt;/div&gt;&lt;div&gt;Simplify by adding nhold_clk_wait&lt;br /&gt;
&lt;br /&gt;
Inverted version is used to feel AND ...&lt;/div&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/clk_delay.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/clk_delay.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/clk_delay.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_reset.do&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_reset.sv&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.v&lt;br /&gt;~ /a-z80/trunk/cpu/registers/test_registers.sv&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/coremodules.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/globals.vh&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 10 Dec 2016 16:06:34 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=16</guid>
        </item>
        <item>
            <title>zxspectrum: Fix few Quartus warnings</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=15</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 15 - gdevic&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;zxspectrum: Fix few Quartus warnings&lt;/div&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/i2s_intf.vhd&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 10 Dec 2016 04:55:23 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=15</guid>
        </item>
        <item>
            <title>Add hold_clk_wait to ALU CFL latch

This correctly delays latching the ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=14</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 14 - gdevic&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;Add hold_clk_wait to ALU CFL latch&lt;br /&gt;
&lt;br /&gt;
This correctly delays latching the ...&lt;/div&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.v&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/coremodules.vh&lt;br /&gt;~ /a-z80/trunk/host/common/uart.v&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 10 Dec 2016 04:16:14 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=14</guid>
        </item>
        <item>
            <title>Full support for nWAIT during M1 and memory cycles
This set ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=13</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 13 - gdevic&lt;/strong&gt; (46 file(s) modified)&lt;/div&gt;&lt;div&gt;Full support for nWAIT during M1 and memory cycles&lt;br /&gt;
This set ...&lt;/div&gt;+ /a-z80/trunk/cpu/bus/data_pins_lattice.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/decode_state.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/execute.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/execute.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_matrix.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_matrix_compiled.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_module.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_zero.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/gencompile.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/memory_ifc.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_reset.do&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_reset.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/timing_macros.i&lt;br /&gt;~ /a-z80/trunk/cpu/export.py&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.v&lt;br /&gt;~ /a-z80/trunk/cpu/registers/test_registers.sv&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/coremodules.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/genfuse.py&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/globals.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_top.do&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/test_fuse.vh&lt;br /&gt;~ /a-z80/trunk/host/basic_de1/basic_de1.qsf&lt;br /&gt;~ /a-z80/trunk/host/basic_de1/basic_de1_fpga.sv&lt;br /&gt;~ /a-z80/trunk/host/basic_de1/basic_de1_ModelSim.sv&lt;br /&gt;~ /a-z80/trunk/host/basic_de1/simulation/modelsim/test_host.mpf&lt;br /&gt;~ /a-z80/trunk/host/basic_de1/simulation/modelsim/wave_host.do&lt;br /&gt;+ /a-z80/trunk/host/common/wait_state.bdf&lt;br /&gt;+ /a-z80/trunk/host/common/wait_state.bsf&lt;br /&gt;+ /a-z80/trunk/host/common/wait_state.v&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/rom/combined.rom&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Fri, 09 Dec 2016 07:38:06 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=13</guid>
        </item>
        <item>
            <title>Explicitly set python to execute within a batch file</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=12</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 12 - gdevic&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Explicitly set python to execute within a batch file&lt;/div&gt;~ /a-z80/trunk/tools/zmac/make_modelsim.bat&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 26 Nov 2016 15:14:24 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=12</guid>
        </item>
        <item>
            <title>zxspectrum improvements:

- Added ZX Spectrum ROM mods as described in ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=11</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 11 - gdevic&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;zxspectrum improvements:&lt;br /&gt;
&lt;br /&gt;
- Added ZX Spectrum ROM mods as described in ...&lt;/div&gt;~ /a-z80/trunk/host/zxspectrum_de1/rom/readme.txt&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/rom/zxspectrum_rom.asm&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qsf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sdc&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Thu, 28 Apr 2016 05:42:19 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=11</guid>
        </item>
        <item>
            <title>zxspectrum: Various improvements

- Fixed keyboard bug (by Bogdan S.)
- Minor ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=10</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 10 - gdevic&lt;/strong&gt; (6 file(s) modified)&lt;/div&gt;&lt;div&gt;zxspectrum: Various improvements&lt;br /&gt;
&lt;br /&gt;
- Fixed keyboard bug (by Bogdan S.)&lt;br /&gt;
- Minor ...&lt;/div&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/ps2_kbd.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/video.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sun, 13 Mar 2016 15:19:09 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=10</guid>
        </item>
        <item>
            <title>Updated documentation</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=9</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 9 - gdevic&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated documentation&lt;/div&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.docx&lt;br /&gt;~ /a-z80/trunk/docs/QuickStart.pdf&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 12 Mar 2016 21:34:30 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=9</guid>
        </item>
        <item>
            <title>z80: Release 4</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=8</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 8 - gdevic&lt;/strong&gt; (318 file(s) modified)&lt;/div&gt;&lt;div&gt;z80: Release 4&lt;/div&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/alu/alu_flags.v&lt;br /&gt;~ /a-z80/trunk/cpu/alu/simulation/modelsim/test_alu.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/address_latch.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/address_latch.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/address_latch.v&lt;br /&gt;~ /a-z80/trunk/cpu/bus/bus_control.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/bus_control.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/bus_control.v&lt;br /&gt;- /a-z80/trunk/cpu/bus/bus_switch.sv&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_switch.v&lt;br /&gt;~ /a-z80/trunk/cpu/bus/data_pins.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/data_pins.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/data_pins.v&lt;br /&gt;~ /a-z80/trunk/cpu/bus/simulation/modelsim/test_bus.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_bus.do&lt;br /&gt;~ /a-z80/trunk/cpu/bus/test_bus.qsf&lt;br /&gt;~ /a-z80/trunk/cpu/bus/test_bus.sv&lt;br /&gt;~ /a-z80/trunk/cpu/bus/test_pins.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/clk_delay.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/execute.bsf&lt;br /&gt;- /a-z80/trunk/cpu/control/execute.sv&lt;br /&gt;+ /a-z80/trunk/cpu/control/execute.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_matrix.vh&lt;br /&gt;+ /a-z80/trunk/cpu/control/exec_matrix_compiled.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_module.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/exec_zero.vh&lt;br /&gt;+ /a-z80/trunk/cpu/control/gencompile.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/genmatrix.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/genref.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/interrupts.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/interrupts.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/interrupts.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/ir.v&lt;br /&gt;- /a-z80/trunk/cpu/control/pla_decode.sv&lt;br /&gt;+ /a-z80/trunk/cpu/control/pla_decode.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/resets.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/sequencer.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/control/sequencer.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/sequencer.v&lt;br /&gt;~ /a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_sequencer.do&lt;br /&gt;+ /a-z80/trunk/cpu/control/temp_wires.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_control.qsf&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_decode.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_interrupts.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_reset.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/test_sequencer.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/Timings.csv&lt;br /&gt;~ /a-z80/trunk/cpu/control/Timings.xlsm&lt;br /&gt;~ /a-z80/trunk/cpu/control/timing_macros.i&lt;br /&gt;+ /a-z80/trunk/cpu/copyleft.txt&lt;br /&gt;- /a-z80/trunk/cpu/deploy&lt;br /&gt;+ /a-z80/trunk/cpu/export.py&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_control.v&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_file.bdf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_file.bsf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/reg_file.v&lt;br /&gt;~ /a-z80/trunk/cpu/registers/simulation/modelsim/test_registers.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/registers/simulation/modelsim/wave_registers.do&lt;br /&gt;~ /a-z80/trunk/cpu/registers/test_regfile.sv&lt;br /&gt;~ /a-z80/trunk/cpu/registers/test_registers.sv&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/core.vh&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/coremodules.vh&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/gencoremodules.py&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/genfuse.py&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/genglobals.py&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/globals.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/test_top.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_top.do&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/test_fuse.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/test_top.sv&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/toplevel.bdf&lt;br /&gt;- /a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/z80_top_direct_n.v&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/a-z80-toplevel.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/address_latch.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/address_mux.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/address_pins.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_bit_select.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_control.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_core.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_flags.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_mux_2.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_mux_2z.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_mux_3z.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_mux_4.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_mux_8.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_prep_daa.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_select.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_shifter_core.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/alu_slice.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/bus_control.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/clk_delay.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/control_pins_n.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/data_pins.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/data_switch.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/data_switch_mask.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/decode_state.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/inc_dec.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/inc_dec_2bit.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/interrupts.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/ir.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/memory_ifc.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/pin_control.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/reg_control.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/reg_file.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/reg_latch.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/resets.pdf&lt;br /&gt;+ /a-z80/trunk/docs/pdf/sequencer.pdf&lt;br /&gt;- /a-z80/trunk/docs/png/z80-address_latch.png&lt;br /&gt;- /a-z80/trunk/docs/png/z80-address_mux.png&lt;br /&gt;~ /a-z80/trunk/docs/png/z80-address_pins.png&lt;br /&gt;~ /a-z80/trunk/docs/png/z80-alu.png&lt;br /&gt;~ /a-z80/trunk/docs/png/z80-alu_bit_select.png&lt;br /&gt;~ /a-z80/trunk/docs/png/z80-alu_control.png&lt;br /&gt;~ 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/&gt;+ /a-z80/trunk/host/zxspectrum_de1/rom/gw03.rom&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/rom/readme.txt&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/rom/tasm.exe&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/rom/tasm80.tab&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/rom/zxspectrum_rom.asm&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/clocks.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/i2c_loader.vhd&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/i2s_intf.vhd&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.ppf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.qip&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.v&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/ps2_kbd.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/ram8.qip&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/ram8.v&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/test_scr.hex&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qpf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qsf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/video.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qpf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qsf&lt;br /&gt;+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv&lt;br /&gt;~ /a-z80/trunk/modelsim_pre_commit.py&lt;br /&gt;~ /a-z80/trunk/modelsim_setup.py&lt;br /&gt;~ /a-z80/trunk/readme.txt&lt;br /&gt;~ /a-z80/trunk/resources/connotate-fuse.bat&lt;br /&gt;~ /a-z80/trunk/resources/connotate-fuse.py&lt;br /&gt;~ /a-z80/trunk/resources/process-pla.py&lt;br /&gt;~ /a-z80/trunk/tools/dongle/daa/simulate-daa.py&lt;br /&gt;~ /a-z80/trunk/tools/dongle/daa/z80-instruction-test-daa.py&lt;br /&gt;~ /a-z80/trunk/tools/dongle/neg/simulate-neg.py&lt;br /&gt;~ /a-z80/trunk/tools/dongle/sbc/simulate-sbc.py&lt;br /&gt;~ /a-z80/trunk/tools/dongle/sbc/simulate-sub.py&lt;br /&gt;~ /a-z80/trunk/tools/readme.txt&lt;br /&gt;~ /a-z80/trunk/tools/z80_pla_checker/source/ClassPLA.cs&lt;br /&gt;~ /a-z80/trunk/tools/z80_pla_checker/z80_pla_checker.exe&lt;br /&gt;+ /a-z80/trunk/tools/zmac/bin2coe.py&lt;br /&gt;+ /a-z80/trunk/tools/zmac/bin2mif.py&lt;br /&gt;~ /a-z80/trunk/tools/zmac/bindump.py&lt;br /&gt;- /a-z80/trunk/tools/zmac/fpga.hex&lt;br /&gt;~ /a-z80/trunk/tools/zmac/hello_world.asm&lt;br /&gt;~ /a-z80/trunk/tools/zmac/make_fpga.bat&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Sat, 12 Mar 2016 19:27:53 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=8</guid>
        </item>
        <item>
            <title>z80: Fixing repeating INIR/OTIR class of instructions</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=7</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 7 - gdevic&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;z80: Fixing repeating INIR/OTIR class of instructions&lt;/div&gt;~ /a-z80/trunk/cpu/control/exec_matrix.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/Timings.csv&lt;br /&gt;~ /a-z80/trunk/cpu/control/Timings.xlsm&lt;br /&gt;~ /a-z80/trunk/cpu/control/timing_macros.i&lt;br /&gt;~ /a-z80/trunk/cpu/deploy/exec_matrix.vh&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Fri, 08 Jan 2016 14:59:26 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=7</guid>
        </item>
        <item>
            <title>Added deployment folder with all files needed to use the ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=6</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 6 - gdevic&lt;/strong&gt; (73 file(s) modified)&lt;/div&gt;&lt;div&gt;Added deployment folder with all files needed to use the ...&lt;/div&gt;~ /a-z80/trunk/cpu/bus/bus_switch.sv&lt;br /&gt;~ /a-z80/trunk/cpu/control/execute.sv&lt;br /&gt;- /a-z80/trunk/cpu/control/exec_matrix.i&lt;br /&gt;+ /a-z80/trunk/cpu/control/exec_matrix.vh&lt;br /&gt;- /a-z80/trunk/cpu/control/exec_module.i&lt;br /&gt;+ /a-z80/trunk/cpu/control/exec_module.vh&lt;br /&gt;- /a-z80/trunk/cpu/control/exec_zero.i&lt;br /&gt;+ /a-z80/trunk/cpu/control/exec_zero.vh&lt;br /&gt;~ /a-z80/trunk/cpu/control/genmatrix.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/genref.py&lt;br /&gt;~ /a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf&lt;br /&gt;~ /a-z80/trunk/cpu/control/timing_macros.i&lt;br /&gt;+ /a-z80/trunk/cpu/deploy&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/address_latch.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/address_mux.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/address_pins.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_bit_select.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_core.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_flags.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_mux_2.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_mux_2z.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_mux_3z.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_mux_4.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_mux_8.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_prep_daa.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_select.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_shifter_core.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/alu_slice.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/bus_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/bus_switch.sv&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/clk_delay.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/control_pins_n.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/core.vh&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/data_pins.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/data_switch.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/data_switch_mask.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/decode_state.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/execute.sv&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/exec_matrix.vh&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/exec_module.vh&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/exec_zero.vh&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/globals.vh&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/inc_dec.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/inc_dec_2bit.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/interrupts.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/ir.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/memory_ifc.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/pin_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/pla_decode.sv&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/readme.txt&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/reg_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/reg_file.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/reg_latch.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/resets.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/sequencer.v&lt;br /&gt;+ /a-z80/trunk/cpu/deploy/z80_top_direct_n.sv&lt;br /&gt;~ /a-z80/trunk/cpu/top-level-files.txt&lt;br /&gt;- /a-z80/trunk/cpu/toplevel/core.i&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/core.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/genfuse.py&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/genglobals.py&lt;br /&gt;- /a-z80/trunk/cpu/toplevel/globals.i&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/globals.vh&lt;br /&gt;- /a-z80/trunk/cpu/toplevel/test_fuse.i&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/test_fuse.sv&lt;br /&gt;+ /a-z80/trunk/cpu/toplevel/test_fuse.vh&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv&lt;br /&gt;~ /a-z80/trunk/cpu/toplevel/z80_top_ifc_n.sv&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.qsf&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Fri, 23 Jan 2015 04:40:58 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=6</guid>
        </item>
        <item>
            <title>zxspectrum: Various improvements

- Added &amp;quot;Turbo&amp;quot; speed mode switch (SW2)
- ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=5</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 5 - gdevic&lt;/strong&gt; (9 file(s) modified)&lt;/div&gt;&lt;div&gt;zxspectrum: Various improvements&lt;br /&gt;
&lt;br /&gt;
- Added &amp;quot;Turbo&amp;quot; speed mode switch (SW2)&lt;br /&gt;
- Turbo ...&lt;/div&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx&lt;br /&gt;~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/rom/readme.txt&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/ula/clocks.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/ula/ula.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/ula/zx_kbd.sv&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.qsf&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.sdc&lt;br /&gt;~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.sv&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Wed, 24 Dec 2014 15:35:08 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=5</guid>
        </item>
        <item>
            <title>- Removed files that are left in the root folder</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=4</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 4 - gdevic&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;- Removed files that are left in the root folder&lt;/div&gt;- /a-z80/.gitignore&lt;br /&gt;- /a-z80/license.txt&lt;br /&gt;- /a-z80/modelsim_pre_commit.py&lt;br /&gt;- /a-z80/modelsim_setup.py&lt;br /&gt;- /a-z80/readme.txt&lt;br /&gt;</description>
            <author>gdevic</author>
            <pubDate>Thu, 18 Dec 2014 14:41:23 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=4</guid>
        </item>
        <item>
            <title>- New directory structure
- Added documentation files (and PDF versions)
- ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=3</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 3 - gdevic&lt;/strong&gt; (456 file(s) modified)&lt;/div&gt;&lt;div&gt;- New directory structure&lt;br /&gt;
- Added documentation files (and PDF versions)&lt;br /&gt;
- ...&lt;/div&gt;- /a-z80/cpu&lt;br /&gt;- /a-z80/docs&lt;br /&gt;- /a-z80/host&lt;br /&gt;- /a-z80/resources&lt;br /&gt;- /a-z80/tools&lt;br /&gt;+ /a-z80/trunk/.gitignore&lt;br /&gt;+ /a-z80/trunk/cpu&lt;br /&gt;+ /a-z80/trunk/cpu/alu&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_bit_select.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_bit_select.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_bit_select.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_control.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_control.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_core.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_core.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_core.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_flags.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_flags.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_flags.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2z.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2z.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_2z.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_3z.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_3z.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_3z.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_4.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_4.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_4.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_8.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_8.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_mux_8.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_prep_daa.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_prep_daa.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_prep_daa.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_select.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_select.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_select.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_shifter_core.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_shifter_core.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_shifter_core.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_slice.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_slice.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/alu_slice.v&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/r&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/test_alu.mpf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_alu.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_core.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_mux_3z.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_prep_daa.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_shifter_core.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_slice.do&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_alu.qpf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_alu.qsf&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_alu.sv&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_core.sv&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_mux_3z.sv&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_prep_daa.sv&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_shifter_core.sv&lt;br /&gt;+ /a-z80/trunk/cpu/alu/test_slice.sv&lt;br /&gt;+ /a-z80/trunk/cpu/bus&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_latch.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_latch.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_latch.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_mux.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_mux.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_mux.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_pins.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_pins.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/address_pins.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_control.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_control.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_control.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_switch.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/bus_switch.sv&lt;br /&gt;+ /a-z80/trunk/cpu/bus/control_pins_n.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/control_pins_n.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/control_pins_n.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_pins.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_pins.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_pins.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch_mask.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch_mask.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/data_switch_mask.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec_2bit.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec_2bit.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/inc_dec_2bit.v&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation/modelsim&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation/modelsim/r&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation/modelsim/test_bus.mpf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_bus.do&lt;br /&gt;+ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_pins.do&lt;br /&gt;+ /a-z80/trunk/cpu/bus/test_bus.qpf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/test_bus.qsf&lt;br /&gt;+ /a-z80/trunk/cpu/bus/test_bus.sv&lt;br /&gt;+ /a-z80/trunk/cpu/bus/test_pins.sv&lt;br /&gt;+ /a-z80/trunk/cpu/control&lt;br /&gt;+ /a-z80/trunk/cpu/control/clk_delay.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/control/clk_delay.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/control/clk_delay.v&lt;br /&gt;+ /a-z80/trunk/cpu/control/decode_state.bdf&lt;br /&gt;+ /a-z80/trunk/cpu/control/decode_state.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/control/decode_state.v&lt;br /&gt;+ /a-z80/trunk/cpu/control/execute.bsf&lt;br /&gt;+ /a-z80/trunk/cpu/control/execute.sv&lt;br /&gt;+ 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            <author>gdevic</author>
            <pubDate>Thu, 18 Dec 2014 14:37:35 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=a-z80&amp;path=%2Fa-z80%2F&amp;rev=3</guid>
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