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        <item>
            <title>fixed missing carry flag for ROR instruction</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=17</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 17 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed missing carry flag for ROR instruction&lt;/div&gt;~ /cpu_lecture/trunk/src/alu.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Mon, 25 Jan 2010 18:41:57 +0100</pubDate>
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            <title>fixed missing RD_M signal for IN instruction</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=16</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 16 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed missing RD_M signal for IN instruction&lt;/div&gt;~ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 16 Jan 2010 17:07:41 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=16</guid>
        </item>
        <item>
            <title>fixed SP auto inc/dec problem</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=15</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 15 - jsauermann&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed SP auto inc/dec problem&lt;/div&gt;~ /cpu_lecture/trunk/src/common.vhd&lt;br /&gt;~ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;~ /cpu_lecture/trunk/src/register_file.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 16 Jan 2010 15:12:28 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=15</guid>
        </item>
        <item>
            <title>fixed wrong Q_RSEL for LDD instruction</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=14</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 14 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed wrong Q_RSEL for LDD instruction&lt;/div&gt;~ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Thu, 14 Jan 2010 18:53:35 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=14</guid>
        </item>
        <item>
            <title>fixed fault in LDD/STD decoding</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=13</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 13 - jsauermann&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed fault in LDD/STD decoding&lt;/div&gt;~ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;~ /cpu_lecture/trunk/src/opc_fetch.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Wed, 13 Jan 2010 18:59:59 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=13</guid>
        </item>
        <item>
            <title>fixed bug in decoding of I/O address for SP</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=12</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 12 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed bug in decoding of I/O address for SP&lt;/div&gt;~ /cpu_lecture/trunk/src/register_file.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Tue, 12 Jan 2010 18:48:59 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=12</guid>
        </item>
        <item>
            <title>fixed fault is BSET/BCLR instruction</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=11</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 11 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed fault is BSET/BCLR instruction&lt;/div&gt;~ /cpu_lecture/trunk/src/alu.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sun, 10 Jan 2010 18:42:17 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=11</guid>
        </item>
        <item>
            <title>wait decoder fault fixed</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=10</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 10 - jsauermann&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;wait decoder fault fixed&lt;/div&gt;~ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;~ /cpu_lecture/trunk/src/opc_fetch.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sun, 10 Jan 2010 13:21:19 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=10</guid>
        </item>
        <item>
            <title>renamed 'main' to 'hello' in build commands</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=9</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 9 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;renamed 'main' to 'hello' in build commands&lt;/div&gt;~ /cpu_lecture/trunk/html/09_Toolchain_Setup.html&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 09 Jan 2010 17:11:29 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=9</guid>
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        <item>
            <title>picture quality slightly improved</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=8</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 8 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;picture quality slightly improved&lt;/div&gt;~ /cpu_lecture/trunk/doc/lecture.pdf&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 09 Jan 2010 12:29:02 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=8</guid>
        </item>
        <item>
            <title>support multiple port sizes in make_mem</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=7</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 7 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;support multiple port sizes in make_mem&lt;/div&gt;+ /cpu_lecture/trunk/gtkwave.save&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 09 Jan 2010 11:15:01 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=7</guid>
        </item>
        <item>
            <title>support multiple port sizes in make_mem</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=6</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 6 - jsauermann&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;support multiple port sizes in make_mem&lt;/div&gt;~ /cpu_lecture/trunk/src/prog_mem.vhd&lt;br /&gt;~ /cpu_lecture/trunk/src/prog_mem_content.vhd&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 09 Jan 2010 10:59:56 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=6</guid>
        </item>
        <item>
            <title>support multiple port sizes in make_mem</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=5</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 5 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;support multiple port sizes in make_mem&lt;/div&gt;~ /cpu_lecture/trunk/tools/make_mem.cc&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Sat, 09 Jan 2010 10:53:40 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=5</guid>
        </item>
        <item>
            <title>initial check-in</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=4</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 4 - jsauermann&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;initial check-in&lt;/div&gt;+ /cpu_lecture/trunk/doc&lt;br /&gt;+ /cpu_lecture/trunk/doc/lecture.pdf&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Tue, 05 Jan 2010 14:38:42 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=4</guid>
        </item>
        <item>
            <title>initial check-in</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=3</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 3 - jsauermann&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;initial check-in&lt;/div&gt;+ /cpu_lecture/trunk/Makefile&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Tue, 05 Jan 2010 09:50:41 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=3</guid>
        </item>
        <item>
            <title>initial check-in</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=2</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 2 - jsauermann&lt;/strong&gt; (88 file(s) modified)&lt;/div&gt;&lt;div&gt;initial check-in&lt;/div&gt;+ /cpu_lecture/trunk/app&lt;br /&gt;+ /cpu_lecture/trunk/app/hello.c&lt;br /&gt;+ /cpu_lecture/trunk/app/hello.lss&lt;br /&gt;+ /cpu_lecture/trunk/app/hello.lss1&lt;br /&gt;+ /cpu_lecture/trunk/html&lt;br /&gt;+ /cpu_lecture/trunk/html/01_Introduction_and_Overview.html&lt;br /&gt;+ /cpu_lecture/trunk/html/02_Top_Level.html&lt;br /&gt;+ /cpu_lecture/trunk/html/03_Pipelining.html&lt;br /&gt;+ /cpu_lecture/trunk/html/04_Cpu_Core.html&lt;br /&gt;+ /cpu_lecture/trunk/html/05_Opcode_Fetch.html&lt;br /&gt;+ /cpu_lecture/trunk/html/06_Data_Path.html&lt;br /&gt;+ /cpu_lecture/trunk/html/07_Opcode_Decoder.html&lt;br /&gt;+ /cpu_lecture/trunk/html/08_IO.html&lt;br /&gt;+ /cpu_lecture/trunk/html/09_Toolchain_Setup.html&lt;br /&gt;+ /cpu_lecture/trunk/html/10_Listing_of_alu_vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/11_Listing_of_avr_fpga.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/12_Listing_of_baudgen.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/13_Listing_of_common.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/14_Listing_of_cpu_core.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/15_Listing_of_data_mem.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/16_Listing_of_data_path.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/17_Listing_of_io.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/18_Listing_of_opc_deco.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/19_Listing_of_opc_fetch.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/20_Listing_of_prog_mem_content.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/21_Listing_of_prog_mem.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/22_Listing_of_reg_16.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/23_Listing_of_register_file.vhd.html&lt;br /&gt;+ /cpu_lecture/trunk/html/24_Listing_of_segment7.vhd.html&lt;br /&gt;+ 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/cpu_lecture/trunk/src/COPYING&lt;br /&gt;+ /cpu_lecture/trunk/src/cpu_core.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/data_mem.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/data_path.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/io.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/opc_deco.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/opc_fetch.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/prog_mem.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/prog_mem_content.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/register_file.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/reg_16.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/segment7.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/status_reg.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/uart.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/uart_rx.vhd&lt;br /&gt;+ /cpu_lecture/trunk/src/uart_tx.vhd&lt;br /&gt;+ /cpu_lecture/trunk/test&lt;br /&gt;+ /cpu_lecture/trunk/test/RAMB4_S4_S4.vhd&lt;br /&gt;+ /cpu_lecture/trunk/test/test_tb.vhd&lt;br /&gt;+ /cpu_lecture/trunk/tools&lt;br /&gt;+ /cpu_lecture/trunk/tools/end_conv.cc&lt;br /&gt;+ /cpu_lecture/trunk/tools/make_mem.cc&lt;br /&gt;+ /cpu_lecture/trunk/work&lt;br /&gt;</description>
            <author>jsauermann</author>
            <pubDate>Mon, 04 Jan 2010 16:51:33 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=2</guid>
        </item>
        <item>
            <title>The project and the structure was created</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=1</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 1 - root&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;The project and the structure was created&lt;/div&gt;+ /cpu_lecture&lt;br /&gt;+ /cpu_lecture/branches&lt;br /&gt;+ /cpu_lecture/tags&lt;br /&gt;+ /cpu_lecture/trunk&lt;br /&gt;</description>
            <author>root</author>
            <pubDate>Mon, 04 Jan 2010 15:40:04 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=cpu_lecture&amp;path=%2Fcpu_lecture%2F&amp;rev=1</guid>
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