OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Error creating feed file, please check write permissions.
t6507lp WebSVN RSS feed - t6507lp https://lists.opencores.org/websvn//websvn/listing?repname=t6507lp&path=%2Ft6507lp%2F& Mon, 22 Jul 2024 17:10:00 +0100 FeedCreator 1.7.2 Timescale was unified. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=113 <div><strong>Rev 113 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Timescale was unified.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br /> gabrieloshiro Wed, 25 Mar 2009 12:47:38 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=113 Created a global timescale file for the project. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=112 <div><strong>Rev 112 - creep</strong> (3 file(s) modified)</div><div>Created a global timescale file for the project.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />+ /t6507lp/trunk/rtl/verilog/timescale.v<br /> creep Wed, 25 Mar 2009 12:43:42 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=112 Performed some linting after coding was finished. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=111 <div><strong>Rev 111 - creep</strong> (2 file(s) modified)</div><div>Performed some linting after coding was finished.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 21:13:19 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=111 All addressing modes and special instructions have been coded and ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=110 <div><strong>Rev 110 - creep</strong> (2 file(s) modified)</div><div>All addressing modes and special instructions have been coded and ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 20:08:34 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=110 PLA and PLP are coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=109 <div><strong>Rev 109 - creep</strong> (2 file(s) modified)</div><div>PLA and PLP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 17:19:01 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=109 PHA and PHP are coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=108 <div><strong>Rev 108 - creep</strong> (2 file(s) modified)</div><div>PHA and PHP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 16:38:32 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=108 The RTS instruction is working fine. Coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=107 <div><strong>Rev 107 - creep</strong> (2 file(s) modified)</div><div>The RTS instruction is working fine. Coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 15:51:50 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=107 First stable version. Things seems to be working. Simulation is ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=106 <div><strong>Rev 106 - gabrieloshiro</strong> (1 file(s) modified)</div><div>First stable version. Things seems to be working. Simulation is ...</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br /> gabrieloshiro Tue, 24 Mar 2009 15:36:35 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=106 The RTI instruction is working fine. Coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=105 <div><strong>Rev 105 - creep</strong> (2 file(s) modified)</div><div>The RTI instruction is working fine. Coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 15:26:03 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=105 The BRK instruction is working. The reset vector was tested ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=104 <div><strong>Rev 104 - creep</strong> (2 file(s) modified)</div><div>The BRK instruction is working. The reset vector was tested ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 24 Mar 2009 13:33:24 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=104 Some early modifications to support the special stack instructions. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=103 <div><strong>Rev 103 - creep</strong> (1 file(s) modified)</div><div>Some early modifications to support the special stack instructions.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br /> creep Mon, 23 Mar 2009 20:03:19 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=103 Some early modifications to support the special stack instructions. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=102 <div><strong>Rev 102 - creep</strong> (2 file(s) modified)</div><div>Some early modifications to support the special stack instructions.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Mon, 23 Mar 2009 17:09:38 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=102 Absolute indirect addressing mode is coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=101 <div><strong>Rev 101 - creep</strong> (2 file(s) modified)</div><div>Absolute indirect addressing mode is coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Mon, 23 Mar 2009 13:42:49 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=101 IDY WRITE TYPE instructions are coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=100 <div><strong>Rev 100 - creep</strong> (2 file(s) modified)</div><div>IDY WRITE TYPE instructions are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Mon, 23 Mar 2009 12:40:58 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=100 Only Package.v should be used. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=99 <div><strong>Rev 99 - creep</strong> (1 file(s) modified)</div><div>Only Package.v should be used.</div>- /t6507lp/trunk/rtl/verilog/T6507LP_Package.h<br /> creep Mon, 23 Mar 2009 12:10:46 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=99 Updated status and some comments. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=98 <div><strong>Rev 98 - creep</strong> (1 file(s) modified)</div><div>Updated status and some comments.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Mon, 23 Mar 2009 12:10:16 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=98 Removed obsolete TODO. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=97 <div><strong>Rev 97 - creep</strong> (1 file(s) modified)</div><div>Removed obsolete TODO.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_Package.v<br /> creep Mon, 23 Mar 2009 12:09:17 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=97 IDY READ TYPE instructions are coded and simulated. IDY WRITE ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=96 <div><strong>Rev 96 - creep</strong> (2 file(s) modified)</div><div>IDY READ TYPE instructions are coded and simulated.<br /> IDY WRITE ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Fri, 20 Mar 2009 20:32:38 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=96 IDX addressing mode is also 100%, coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=95 <div><strong>Rev 95 - creep</strong> (2 file(s) modified)</div><div>IDX addressing mode is also 100%, coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Fri, 20 Mar 2009 16:54:42 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=95 Relative addressing mode is almost 100% functional. It just needs another ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=94 <div><strong>Rev 94 - creep</strong> (2 file(s) modified)</div><div>Relative addressing mode is almost 100% functional.<br /> It just needs another ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Thu, 19 Mar 2009 20:18:00 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=94
© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.