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t6507lp WebSVN RSS feed - t6507lp https://lists.opencores.org/websvn//websvn/listing?repname=t6507lp&path=%2Ft6507lp%2F& Tue, 14 Apr 2026 02:38:32 +0100 FeedCreator 1.7.2 Decimal mode (BCD) is working. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=81 <div><strong>Rev 81 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Decimal mode (BCD) is working.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br /> gabrieloshiro Tue, 17 Mar 2009 20:02:58 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=81 Grouping some instructions that have the same behavioral. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=80 <div><strong>Rev 80 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Grouping some instructions that have the same behavioral.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br /> gabrieloshiro Tue, 17 Mar 2009 19:27:11 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=80 ALU testbench added. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=79 <div><strong>Rev 79 - gabrieloshiro</strong> (6 file(s) modified)</div><div>ALU testbench added.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />+ /t6507lp/trunk/sim<br />+ /t6507lp/trunk/sim/T6507LP_ULA<br />+ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br />+ /t6507lp/trunk/syn<br />+ /t6507lp/trunk/syn/xilinx<br /> gabrieloshiro Tue, 17 Mar 2009 18:35:44 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=79 ZPG coded and simulated. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=78 <div><strong>Rev 78 - creep</strong> (2 file(s) modified)</div><div>ZPG coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 17 Mar 2009 18:26:36 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=78 ZPG coded. Simulation is halfway. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=77 <div><strong>Rev 77 - creep</strong> (1 file(s) modified)</div><div>ZPG coded. Simulation is halfway.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br /> creep Tue, 17 Mar 2009 17:49:35 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=77 ABS write instructions were not simulated. Also added some initial ZPG ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=76 <div><strong>Rev 76 - creep</strong> (1 file(s) modified)</div><div>ABS write instructions were not simulated.<br /> Also added some initial ZPG ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 17 Mar 2009 17:48:50 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=76 First working version! https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=75 <div><strong>Rev 75 - gabrieloshiro</strong> (2 file(s) modified)</div><div>First working version!</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br /> gabrieloshiro Tue, 17 Mar 2009 17:39:53 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=75 The file now describes who is doing what. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=74 <div><strong>Rev 74 - creep</strong> (1 file(s) modified)</div><div>The file now describes who is doing what.</div>~ /t6507lp/trunk/README.TXT<br /> creep Tue, 17 Mar 2009 17:14:15 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=74 Added schedule file into the readme file. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=73 <div><strong>Rev 73 - creep</strong> (1 file(s) modified)</div><div>Added schedule file into the readme file.</div>~ /t6507lp/README.TXT<br /> creep Tue, 17 Mar 2009 17:12:41 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=73 Project management folder. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=72 <div><strong>Rev 72 - creep</strong> (2 file(s) modified)</div><div>Project management folder.</div>+ /t6507lp/trunk/mngmt<br />+ /t6507lp/trunk/mngmt/atari.pod<br /> creep Tue, 17 Mar 2009 17:09:53 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=72 Four addressing modes are simulated: immediate, accumulator, implied and absolute. The ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=71 <div><strong>Rev 71 - creep</strong> (2 file(s) modified)</div><div>Four addressing modes are simulated: immediate, accumulator, implied and absolute.<br /> The ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Tue, 17 Mar 2009 17:04:28 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=71 Fixed several timing. Registered outputs working. Only three adressing modes coded, ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=70 <div><strong>Rev 70 - creep</strong> (1 file(s) modified)</div><div>Fixed several timing. Registered outputs working.<br /> Only three adressing modes coded, ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br /> creep Fri, 13 Mar 2009 20:37:21 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=70 Added signal origin/destination. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=69 <div><strong>Rev 69 - creep</strong> (1 file(s) modified)</div><div>Added signal origin/destination.</div>~ /t6507lp/trunk/doc/spec.odt<br /> creep Fri, 13 Mar 2009 18:52:18 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=69 The FSM module is now parametrized. Also, several changes were made ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=68 <div><strong>Rev 68 - creep</strong> (2 file(s) modified)</div><div>The FSM module is now parametrized.<br /> Also, several changes were made ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Fri, 13 Mar 2009 18:16:34 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=68 File name change to lowercase. HAL says so! https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=67 <div><strong>Rev 67 - creep</strong> (1 file(s) modified)</div><div>File name change to lowercase. HAL says so!</div>+ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br /> creep Fri, 13 Mar 2009 16:25:49 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=67 File name change to lowercase. HAL says so! https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=66 <div><strong>Rev 66 - creep</strong> (1 file(s) modified)</div><div>File name change to lowercase. HAL says so!</div>- /t6507lp/trunk/rtl/verilog/T6507LP_FSM_TB.v<br /> creep Fri, 13 Mar 2009 16:25:31 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=66 Now the blocks are connected. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=65 <div><strong>Rev 65 - gabrieloshiro</strong> (1 file(s) modified)</div><div>Now the blocks are connected.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br /> gabrieloshiro Thu, 12 Mar 2009 21:26:36 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=65 Constant were wrong. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=64 <div><strong>Rev 64 - gabrieloshiro</strong> (1 file(s) modified)</div><div>Constant were wrong.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_Package.v<br /> gabrieloshiro Thu, 12 Mar 2009 21:19:43 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=64 Fixed several HAL warnings. Still plenty to do. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=63 <div><strong>Rev 63 - creep</strong> (1 file(s) modified)</div><div>Fixed several HAL warnings. Still plenty to do.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br /> creep Thu, 12 Mar 2009 21:15:42 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=63 The DUT file name changed. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=62 <div><strong>Rev 62 - creep</strong> (1 file(s) modified)</div><div>The DUT file name changed.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_FSM_TB.v<br /> creep Thu, 12 Mar 2009 21:15:15 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2F&rev=62

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