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        <item>
            <title>ADC bugs finally fixed.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=169</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 169 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;ADC bugs finally fixed.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 20:35:54 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=169</guid>
        </item>
        <item>
            <title>RTI fixed! now ALU doesn`t support RTI instruction anymore.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=168</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 168 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;RTI fixed! now ALU doesn`t support RTI instruction anymore.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 19:21:09 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=168</guid>
        </item>
        <item>
            <title>Now SBC is supposed to work.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=167</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 167 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Now SBC is supposed to work.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 18:44:54 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=167</guid>
        </item>
        <item>
            <title>Commiting again!</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=166</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 166 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Commiting again!&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 18:34:53 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=166</guid>
        </item>
        <item>
            <title>SBC and PHP fixed!</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=165</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 165 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;SBC and PHP fixed!&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 18:28:14 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=165</guid>
        </item>
        <item>
            <title>ADC with decimal mode bug... is it ok now?</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=164</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 164 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;ADC with decimal mode bug... is it ok now?&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 17:20:30 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=164</guid>
        </item>
        <item>
            <title>Still having bugs on ADC with decimal flag! Is it ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=163</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 163 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Still having bugs on ADC with decimal flag! Is it ...&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 16:21:24 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=163</guid>
        </item>
        <item>
            <title>ADC with decimal mode ON, bug fixed!</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=162</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 162 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;ADC with decimal mode ON, bug fixed!&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 16:16:28 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=162</guid>
        </item>
        <item>
            <title>Sum and subtract were wrong when D flag was HIGH.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=161</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 161 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Sum and subtract were wrong when D flag was HIGH.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Mon, 06 Apr 2009 15:29:51 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=161</guid>
        </item>
        <item>
            <title>ROL is coded. ADC decimal mode is being re-checked.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=160</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 160 - creep&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;ROL is coded. ADC decimal mode is being re-checked.&lt;/div&gt;~ /t6507lp/trunk/fv/alu_chk.e&lt;br /&gt;~ /t6507lp/trunk/fv/alu_opcodes.e&lt;br /&gt;</description>
            <author>creep</author>
            <pubDate>Mon, 06 Apr 2009 15:09:16 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=160</guid>
        </item>
        <item>
            <title>Checker was extended. All the instructions from A-P are verified. ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=159</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 159 - creep&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Checker was extended. All the instructions from A-P are verified. ...&lt;/div&gt;~ /t6507lp/trunk/fv/alu_chk.e&lt;br /&gt;~ /t6507lp/trunk/fv/alu_opcodes.e&lt;br /&gt;</description>
            <author>creep</author>
            <pubDate>Fri, 03 Apr 2009 19:22:28 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=159</guid>
        </item>
        <item>
            <title>Bug 28 fixed. PHA was not coping the register to ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=158</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 158 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Bug 28 fixed. PHA was not coping the register to ...&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Fri, 03 Apr 2009 19:05:40 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=158</guid>
        </item>
        <item>
            <title>...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=157</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 157 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;...&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Fri, 03 Apr 2009 18:40:30 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=157</guid>
        </item>
        <item>
            <title>Some bugs were fixed. Testbench were expecting wrong values sometimes.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=156</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 156 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Some bugs were fixed. Testbench were expecting wrong values sometimes.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Fri, 03 Apr 2009 17:06:13 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=156</guid>
        </item>
        <item>
            <title>Fixing ticket 25, B flag.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=155</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 155 - creep&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixing ticket 25, B flag.&lt;/div&gt;~ /t6507lp/trunk/fv/alu_chk.e&lt;br /&gt;~ /t6507lp/trunk/fv/alu_opcodes.e&lt;br /&gt;</description>
            <author>creep</author>
            <pubDate>Fri, 03 Apr 2009 12:40:53 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=155</guid>
        </item>
        <item>
            <title>BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=154</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 154 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;BRK_IMP was asserting 0 to B flag.&lt;br /&gt;
&lt;br /&gt;
Bug report #25 fixed.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Fri, 03 Apr 2009 12:34:58 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=154</guid>
        </item>
        <item>
            <title>Added a few more instructions to the checker. Removed prints ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=153</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 153 - creep&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a few more instructions to the checker. Removed prints ...&lt;/div&gt;~ /t6507lp/trunk/fv/alu_chk.e&lt;br /&gt;~ /t6507lp/trunk/fv/alu_opcodes.e&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_wrapper.v&lt;br /&gt;</description>
            <author>creep</author>
            <pubDate>Thu, 02 Apr 2009 19:01:33 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=153</guid>
        </item>
        <item>
            <title>Bug #24 from trac was fixed.</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=152</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 152 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Bug #24 from trac was fixed.&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Thu, 02 Apr 2009 18:39:54 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=152</guid>
        </item>
        <item>
            <title>tah comitado!</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=151</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 151 - gabrieloshiro&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;tah comitado!&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Thu, 02 Apr 2009 17:51:26 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=151</guid>
        </item>
        <item>
            <title>Bug #24 from trac might be fixed. Processor register is ...</title>
            <link>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=150</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 150 - gabrieloshiro&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Bug #24 from trac might be fixed. Processor register is ...&lt;/div&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu.v&lt;br /&gt;~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v&lt;br /&gt;</description>
            <author>gabrieloshiro</author>
            <pubDate>Thu, 02 Apr 2009 17:49:12 +0100</pubDate>
            <guid>https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&amp;path=%2Ft6507lp%2Ftrunk%2F&amp;rev=150</guid>
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