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https://lists.opencores.org/websvn//websvn/listing?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&
Wed, 11 Mar 2026 19:30:40 +0100FeedCreator 1.7.2Changed the module instantiation into the dot form.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=116
<div><strong>Rev 116 - creep</strong> (1 file(s) modified)</div><div>Changed the module instantiation into the dot form.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepWed, 25 Mar 2009 13:13:20 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=116Renamed the signal control. It is mem_rw now.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=115
<div><strong>Rev 115 - creep</strong> (3 file(s) modified)</div><div>Renamed the signal control. It is mem_rw now.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepWed, 25 Mar 2009 13:09:29 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=115Created a global timescale file for the project. Added to ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=114
<div><strong>Rev 114 - creep</strong> (1 file(s) modified)</div><div>Created a global timescale file for the project. Added to ...</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />creepWed, 25 Mar 2009 12:54:25 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=114Timescale was unified.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=113
<div><strong>Rev 113 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Timescale was unified.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br />gabrieloshiroWed, 25 Mar 2009 12:47:38 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=113Created a global timescale file for the project.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=112
<div><strong>Rev 112 - creep</strong> (3 file(s) modified)</div><div>Created a global timescale file for the project.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />+ /t6507lp/trunk/rtl/verilog/timescale.v<br />creepWed, 25 Mar 2009 12:43:42 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=112Performed some linting after coding was finished.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=111
<div><strong>Rev 111 - creep</strong> (2 file(s) modified)</div><div>Performed some linting after coding was finished.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 21:13:19 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=111All addressing modes and special instructions have been coded and ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=110
<div><strong>Rev 110 - creep</strong> (2 file(s) modified)</div><div>All addressing modes and special instructions have been coded and ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 20:08:34 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=110PLA and PLP are coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=109
<div><strong>Rev 109 - creep</strong> (2 file(s) modified)</div><div>PLA and PLP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 17:19:01 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=109PHA and PHP are coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=108
<div><strong>Rev 108 - creep</strong> (2 file(s) modified)</div><div>PHA and PHP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 16:38:32 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=108The RTS instruction is working fine. Coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=107
<div><strong>Rev 107 - creep</strong> (2 file(s) modified)</div><div>The RTS instruction is working fine. Coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 15:51:50 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=107First stable version. Things seems to be working. Simulation is ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=106
<div><strong>Rev 106 - gabrieloshiro</strong> (1 file(s) modified)</div><div>First stable version. Things seems to be working. Simulation is ...</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />gabrieloshiroTue, 24 Mar 2009 15:36:35 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=106The RTI instruction is working fine. Coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=105
<div><strong>Rev 105 - creep</strong> (2 file(s) modified)</div><div>The RTI instruction is working fine. Coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 15:26:03 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=105The BRK instruction is working. The reset vector was tested ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=104
<div><strong>Rev 104 - creep</strong> (2 file(s) modified)</div><div>The BRK instruction is working. The reset vector was tested ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 13:33:24 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=104Some early modifications to support the special stack instructions.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=103
<div><strong>Rev 103 - creep</strong> (1 file(s) modified)</div><div>Some early modifications to support the special stack instructions.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />creepMon, 23 Mar 2009 20:03:19 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=103Some early modifications to support the special stack instructions.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=102
<div><strong>Rev 102 - creep</strong> (2 file(s) modified)</div><div>Some early modifications to support the special stack instructions.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepMon, 23 Mar 2009 17:09:38 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=102Absolute indirect addressing mode is coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=101
<div><strong>Rev 101 - creep</strong> (2 file(s) modified)</div><div>Absolute indirect addressing mode is coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepMon, 23 Mar 2009 13:42:49 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=101IDY WRITE TYPE instructions are coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=100
<div><strong>Rev 100 - creep</strong> (2 file(s) modified)</div><div>IDY WRITE TYPE instructions are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepMon, 23 Mar 2009 12:40:58 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=100Only Package.v should be used.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=99
<div><strong>Rev 99 - creep</strong> (1 file(s) modified)</div><div>Only Package.v should be used.</div>- /t6507lp/trunk/rtl/verilog/T6507LP_Package.h<br />creepMon, 23 Mar 2009 12:10:46 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=99Updated status and some comments.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=98
<div><strong>Rev 98 - creep</strong> (1 file(s) modified)</div><div>Updated status and some comments.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepMon, 23 Mar 2009 12:10:16 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=98Removed obsolete TODO.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=97
<div><strong>Rev 97 - creep</strong> (1 file(s) modified)</div><div>Removed obsolete TODO.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_Package.v<br />creepMon, 23 Mar 2009 12:09:17 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=97
