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t6507lp WebSVN RSS feed - t6507lp https://lists.opencores.org/websvn//websvn/listing?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F& Thu, 25 Jul 2024 13:09:43 +0100 FeedCreator 1.7.2 ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=38 <div><strong>Rev 38 - root</strong> (8 file(s) modified)</div><div>...</div>- /branches<br />+ /t6507lp<br />+ /t6507lp/branches<br />+ /t6507lp/tags<br />+ /t6507lp/trunk<br />+ /t6507lp/web_uploads<br />- /tags<br />- /trunk<br /> root Tue, 10 Mar 2009 18:28:18 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2F&rev=38 Some minor fixes. Now we are trying to make it ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=37 <div><strong>Rev 37 - gabrieloshiro</strong> (4 file(s) modified)</div><div>Some minor fixes. Now we are trying to make it ...</div>~ /trunk/rtl/verilog/T6507LP.v<br />~ /trunk/rtl/verilog/T6507LP_ALU.v<br />~ /trunk/rtl/verilog/T6507LP_FSM.v<br />+ /trunk/rtl/verilog/T6507LP_Package.h<br /> gabrieloshiro Mon, 09 Mar 2009 21:26:40 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=37 All module names are written using uppercase letters now. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=36 <div><strong>Rev 36 - gabrieloshiro</strong> (3 file(s) modified)</div><div>All module names are written using uppercase letters now.</div>~ /trunk/rtl/verilog/T6507LP.v<br />~ /trunk/rtl/verilog/T6507LP_ALU.v<br />~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> gabrieloshiro Mon, 09 Mar 2009 20:55:51 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=36 Several wires created to help code readibility. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=35 <div><strong>Rev 35 - creep</strong> (1 file(s) modified)</div><div>Several wires created to help code readibility.</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 20:46:50 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=35 Fixed state names. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=34 <div><strong>Rev 34 - creep</strong> (1 file(s) modified)</div><div>Fixed state names.</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 18:58:34 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=34 Some portion of the absolute indexed mode is done, yet ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=33 <div><strong>Rev 33 - creep</strong> (1 file(s) modified)</div><div>Some portion of the absolute indexed mode is done, yet ...</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 18:49:07 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=33 Documentation is wrong. I`ve just kept the standard. Some ALU ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=32 <div><strong>Rev 32 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Documentation is wrong. I`ve just kept the standard. Some ALU ...</div>~ /trunk/rtl/verilog/T6507LP.v<br />~ /trunk/rtl/verilog/T6507LP_ALU.v<br /> gabrieloshiro Mon, 09 Mar 2009 18:43:27 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=32 Added zero page indexed mode. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=31 <div><strong>Rev 31 - creep</strong> (1 file(s) modified)</div><div>Added zero page indexed mode.</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 17:53:28 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=31 Added zero page mode. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=30 <div><strong>Rev 30 - creep</strong> (1 file(s) modified)</div><div>Added zero page mode.</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 17:31:15 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=30 Absolute addressing mode should be working. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=29 <div><strong>Rev 29 - creep</strong> (1 file(s) modified)</div><div>Absolute addressing mode should be working.</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 16:30:46 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=29 More documentation. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=28 <div><strong>Rev 28 - gabrieloshiro</strong> (1 file(s) modified)</div><div>More documentation.</div>~ /trunk/rtl/verilog/T6507LP_Package.v<br /> gabrieloshiro Mon, 09 Mar 2009 15:45:29 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=28 Added the pipelining support for a few addressing modes. Still ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=27 <div><strong>Rev 27 - creep</strong> (1 file(s) modified)</div><div>Added the pipelining support for a few addressing modes. Still ...</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Mon, 09 Mar 2009 15:43:46 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=27 I`m still finishing the documentation. But the file should work ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=26 <div><strong>Rev 26 - gabrieloshiro</strong> (1 file(s) modified)</div><div>I`m still finishing the documentation. But the file should work ...</div>~ /trunk/rtl/verilog/T6507LP_Package.v<br /> gabrieloshiro Fri, 06 Mar 2009 22:06:43 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=26 Package file contains all important constants and local parameters. It ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=25 <div><strong>Rev 25 - gabrieloshiro</strong> (1 file(s) modified)</div><div>Package file contains all important constants and local parameters. It ...</div>+ /trunk/rtl/verilog/T6507LP_Package.v<br /> gabrieloshiro Fri, 06 Mar 2009 20:23:18 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=25 Added some simple logic to a few states. Connection with ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=24 <div><strong>Rev 24 - creep</strong> (1 file(s) modified)</div><div>Added some simple logic to a few states. Connection with ...</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Fri, 06 Mar 2009 19:58:07 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=24 Updated file header standard. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=23 <div><strong>Rev 23 - creep</strong> (3 file(s) modified)</div><div>Updated file header standard.</div>~ /trunk/doc/file_header_standard.txt<br />~ /trunk/rtl/verilog/T6507LP_ALU.v<br />~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Fri, 06 Mar 2009 18:57:12 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=23 Signal and module name convention. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=22 <div><strong>Rev 22 - creep</strong> (1 file(s) modified)</div><div>Signal and module name convention.</div>~ /trunk/rtl/verilog/T6507LP.v<br /> creep Fri, 06 Mar 2009 18:55:24 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=22 *** empty log message *** https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=21 <div><strong>Rev 21 - creep</strong> (1 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Fri, 06 Mar 2009 18:52:23 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=21 Added immediate, absolute and zero page addressing modes FSM branches. ... https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=20 <div><strong>Rev 20 - creep</strong> (1 file(s) modified)</div><div>Added immediate, absolute and zero page addressing modes FSM branches. ...</div>~ /trunk/rtl/verilog/T6507LP_FSM.v<br /> creep Fri, 06 Mar 2009 17:56:59 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=20 Parameters removed. https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=19 <div><strong>Rev 19 - creep</strong> (1 file(s) modified)</div><div>Parameters removed.</div>~ /trunk/rtl/verilog/T6507LP_ALU.v<br /> creep Fri, 06 Mar 2009 16:55:44 +0100 https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ftrunk%2Frtl%2F&rev=19
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