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https://lists.opencores.org/websvn//websvn/listing?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&
Tue, 19 May 2026 01:46:09 +0100FeedCreator 1.7.2t6507lp_package.v was renamed to avoid uppercase.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=139
<div><strong>Rev 139 - creep</strong> (2 file(s) modified)</div><div>t6507lp_package.v was renamed to avoid uppercase.</div>+ /t6507lp/trunk/rtl/verilog/t6507lp_package.v<br />- /t6507lp/trunk/rtl/verilog/T6507LP_Package.v<br />creepWed, 01 Apr 2009 13:43:08 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=139Some minor coding style changes.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=136
<div><strong>Rev 136 - gabrieloshiro</strong> (4 file(s) modified)</div><div>Some minor coding style changes.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp.v<br />~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />+ /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v<br />- /t6507lp/trunk/rtl/verilog/T6507LP_ALU_TestBench.v<br />gabrieloshiroTue, 31 Mar 2009 17:31:29 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=136RTL and e files are truly linked now. Some very ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=129
<div><strong>Rev 129 - creep</strong> (7 file(s) modified)</div><div>RTL and e files are truly linked now. Some very ...</div>~ /t6507lp/trunk/fv/alu_agent.e<br />~ /t6507lp/trunk/fv/alu_bfm.e<br />~ /t6507lp/trunk/fv/alu_components.e<br />~ /t6507lp/trunk/fv/alu_env.e<br />~ /t6507lp/trunk/fv/alu_sigmap.e<br />~ /t6507lp/trunk/fv/alu_sync.e<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_alu_wrapper.v<br />creepFri, 27 Mar 2009 18:18:17 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=129$write and $finish primitives were removed from synthesizable blocks. Latches ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=128
<div><strong>Rev 128 - gabrieloshiro</strong> (3 file(s) modified)</div><div>$write and $finish primitives were removed from synthesizable blocks. Latches ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp.v<br />~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />gabrieloshiroFri, 27 Mar 2009 14:28:52 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=128Testbench created. Simulation is almost done! Everything seems to be ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=127
<div><strong>Rev 127 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Testbench created. Simulation is almost done! Everything seems to be ...</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />+ /t6507lp/trunk/rtl/verilog/T6507LP_ALU_TestBench.v<br />gabrieloshiroFri, 27 Mar 2009 13:31:53 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=127Added a wrapper for the ALU. This file creates the ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=126
<div><strong>Rev 126 - creep</strong> (2 file(s) modified)</div><div>Added a wrapper for the ALU. This file creates the ...</div>~ /t6507lp/trunk/fv/alu_sigmap.e<br />+ /t6507lp/trunk/rtl/verilog/t6507lp_alu_wrapper.v<br />creepFri, 27 Mar 2009 13:01:27 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=126Added some extra commentaries.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=120
<div><strong>Rev 120 - creep</strong> (1 file(s) modified)</div><div>Added some extra commentaries.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />creepWed, 25 Mar 2009 17:51:42 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=120removing old file.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=119
<div><strong>Rev 119 - creep</strong> (1 file(s) modified)</div><div>removing old file.</div>- /t6507lp/trunk/rtl/verilog/T6507LP.v<br />creepWed, 25 Mar 2009 15:10:49 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=119The top level name was in uppercase. The correct is ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=118
<div><strong>Rev 118 - creep</strong> (1 file(s) modified)</div><div>The top level name was in uppercase. The correct is ...</div>+ /t6507lp/trunk/rtl/verilog/t6507lp.v<br />creepWed, 25 Mar 2009 13:43:53 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=118Fixed the top level and connected the entire project.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=117
<div><strong>Rev 117 - creep</strong> (3 file(s) modified)</div><div>Fixed the top level and connected the entire project.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepWed, 25 Mar 2009 13:42:51 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=117Changed the module instantiation into the dot form.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=116
<div><strong>Rev 116 - creep</strong> (1 file(s) modified)</div><div>Changed the module instantiation into the dot form.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepWed, 25 Mar 2009 13:13:20 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=116Renamed the signal control. It is mem_rw now.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=115
<div><strong>Rev 115 - creep</strong> (3 file(s) modified)</div><div>Renamed the signal control. It is mem_rw now.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepWed, 25 Mar 2009 13:09:29 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=115Created a global timescale file for the project. Added to ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=114
<div><strong>Rev 114 - creep</strong> (1 file(s) modified)</div><div>Created a global timescale file for the project. Added to ...</div>~ /t6507lp/trunk/rtl/verilog/T6507LP.v<br />creepWed, 25 Mar 2009 12:54:25 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=114Timescale was unified.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=113
<div><strong>Rev 113 - gabrieloshiro</strong> (2 file(s) modified)</div><div>Timescale was unified.</div>~ /t6507lp/trunk/rtl/verilog/T6507LP_ALU.v<br />~ /t6507lp/trunk/sim/T6507LP_ULA/T6507LP_ALU_TestBench.v<br />gabrieloshiroWed, 25 Mar 2009 12:47:38 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=113Created a global timescale file for the project.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=112
<div><strong>Rev 112 - creep</strong> (3 file(s) modified)</div><div>Created a global timescale file for the project.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />+ /t6507lp/trunk/rtl/verilog/timescale.v<br />creepWed, 25 Mar 2009 12:43:42 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=112Performed some linting after coding was finished.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=111
<div><strong>Rev 111 - creep</strong> (2 file(s) modified)</div><div>Performed some linting after coding was finished.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 21:13:19 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=111All addressing modes and special instructions have been coded and ...
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=110
<div><strong>Rev 110 - creep</strong> (2 file(s) modified)</div><div>All addressing modes and special instructions have been coded and ...</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 20:08:34 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=110PLA and PLP are coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=109
<div><strong>Rev 109 - creep</strong> (2 file(s) modified)</div><div>PLA and PLP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 17:19:01 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=109PHA and PHP are coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=108
<div><strong>Rev 108 - creep</strong> (2 file(s) modified)</div><div>PHA and PHP are coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 16:38:32 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=108The RTS instruction is working fine. Coded and simulated.
https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=107
<div><strong>Rev 107 - creep</strong> (2 file(s) modified)</div><div>The RTS instruction is working fine. Coded and simulated.</div>~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v<br />~ /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v<br />creepTue, 24 Mar 2009 15:51:50 +0100https://lists.opencores.org/websvn//websvn/revision?repname=t6507lp&path=%2Ft6507lp%2Ftrunk%2Frtl%2Fverilog%2F&rev=107
